CAT28LV65 Datasheet, PDF (8/15 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL E2PROM

CAT28LV65
DATA Polling
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is initiated,
attempting to read the last byte written will output the
complement of that data on I/O₇ (I/O₀–I/O ₆ are
indeterminate) until the programming cycle is complete.
Upon completion of the self−timed write cycle, all I/O’s will
output true data during a read cycle.
Toggle Bit
In addition to the DATA Polling feature, the device offers
an additional method for determining the completion of a
write cycle. While a write cycle is in progress, reading data
from the device will result in I/O₆ toggling between one and
zero. However, once the write is complete, I/O₆ stops
toggling and valid data can be read from the device.
Ready/BUSY (RDY/BUSY)
The RDY/BUSY pin is an open drain output which
indicates device status during programming. It is pulled low
during the write cycle and released at the end of
programming. Several devices may be OR−tied to the same
RDY/BUSY line.
ADDRESS
CE
WE
OE
I/O7
D_IN = X
t_OEH
t_OE
t_WC
D_OUT = X
Figure 8. DATA Polling
t_OES
D_OUT = X
WE
CE
t_OEH
t_OE
OE
I/O₆
(Note 13)
t_WC
Figure 9. Toggle Bit
13. Beginning and ending state of I/O₆ is indeterminate.
t_OES
(Note 13)
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