CAT28LV65 Datasheet, PDF (7/15 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL E2PROM

CAT28LV65
Page Write
The page write mode of the CAT28LV65 (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes of
data to be programmed within a single EEPROM write
cycle. This effectively reduces the byte−write time by a
factor of 32.
Following an initial WRITE operation (WE pulsed low,
for t_WP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address and
data bytes into a 32 byte temporary buffer. The page address
where data is to be written, specified by bits A₅ to A₁₂, is
latched on the last falling edge of WE. Each byte within the
page is defined by address bits A₀ to A₄ (which can be loaded
ADDRESS
in any order) during the first and subsequent write cycles.
Each successive byte load cycle must begin within t_{BLC MAX}
of the rising edge of the preceding WE pulse. There is no
page write window limitation as long as WE is pulsed low
within t_{BLC MAX}.
Upon completion of the page write sequence, WE must
stay high a minimum of t_{BLC MAX} for the internal automatic
program cycle to commence. This programming cycle
consists of an erase cycle, which erases any data that existed
in each addressed cell, and a write cycle, which writes new
data back into the cell. A page write will only write data to
the locations that were addressed and will not rewrite the
entire page.
t_WC
t_AS
CE
t_AH
t_CW
t_BLC
t_OEH
OE
t_OES
t_CS
t_CH
WE
t_RB
HIGH−Z
RDY/BUSY
HIGH−Z
DATA OUT
HIGH−Z
DATA IN
DATA VALID
t_DS
t_DH
Figure 6. Byte Write Cycle [CE Controlled]
OE
CE
t_WP
t_BLC
WE
ADDRESS
I/O
BYTE 0 BYTE 1
BYTE 2
BYTE n
Figure 7. Page Mode Write Cycle
BYTE n+1
t_WC
LAST BYTE
BYTE n+2
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