CAT28LV65 Datasheet, PDF (5/15 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL E2PROM

CAT28LV65
V_CC − 0.3 V
0.0 V
INPUT PULSE LEVELS
2.0 V
0.6 V
REFERENCE POINTS
Figure 2. A.C. Testing Input/Output Waveform (Note 9)
9. Input rise and fall times (10% and 90%) < 10 ns.
V_CC
DEVICE
UNDER
TEST
1.8 K
1. 3 K
OUTPUT
C_L = 100 pF
C_L INCLUDES JIG CAPACITANCE
Figure 3. A.C. Testing Load Circuit (example)
Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (V_CC = 3.0 V to 3.6 V, unless otherwise specified.)
28LV65−15
28LV65−20
28LV65−25
Symbol
Parameter
Min
Max
Min
Max
Min
Max Units
t_WC
Write Cycle Time
t_AS
Address Setup Time
t_AH
Address Hold Time
t_CS
CE Setup Time
5
5
5
ms
0
0
0
ns
100
100
100
ns
0
0
0
ns
t_CH
t_CW (Note 10)
t_OES
t_OEH
t_WP (Note 10)
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
0
0
0
ns
110
150
150
ns
0
10
10
ns
0
10
10
ns
110
150
150
ns
t_DS
Data Setup Time
60
100
100
ns
t_DH
Data Hold Time
0
0
0
ns
t_INIT (Note 11)
Write Inhibit Period After Power−up
5
10
5
10
5
10
ms
t_BLC (Notes 11, 12) Byte Load Cycle Time
0.05
100
0.1
100
0.1
100
ms
t_RB
WE Low to RDY/BUSY Low
220
220
220
ns
10. A write pulse of less than 20 ns duration will not initiate a write cycle.
11. This parameter is tested initially and after a design or process change that affects the parameter.
12. A timer of duration t_BLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however
a transition from HIGH to LOW within t_BLC max. stops the timer.
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