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AR0230 Datasheet, PDF (8/36 Pages) ON Semiconductor – Full HD Digital Image Sensor | |||
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AR0230CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor
Functional Overview
Figure 2:
high dynamic range mode of operation where multiple images are combined on-chip to
produce a single image at 16-bit per pixel value. A compression mode is further offered
to allow the 16 bits per pixel to be transmitted to the host system as a 12-bit value with
close to zero loss in image quality.
Typical Configuration: Serial Four-Lane HiSPi Interface
Digital Digital
I/O Core
power1 power1
HiSPi
PLL Analog Analog
power1 power1 power1 power1
Master clock
(6â48 MHz)
From
controller
VDD_IO VDD
EXTCLK
SADDR
SDATA
SCLK
TRIGGER
OE_BAR
RESET_BAR
TEST
DGND
VDD_PLL VAA VAA_PIX
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
SLVS3_P
SLVS3_N
SLVSC_P
SLVSC_N
FLASH
SHUTTER
AGND
To
controller
VDD_IO
VDD
VDD_SLVS VDD_PLL
VAA
VAA_PIX
Digital
ground
Analog
ground
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5kï, but a greater value may be used for
slower two-wire speed.
3. The parallel interface output pads can be left unconnected if the serial output interface is used.
4. ON Semiconductor recommends that 0.1ïF and 10ïF decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on lay-
out and design considerations. Refer to the AR0230CS demo headboard schematics for circuit rec-
ommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-
pling with the digital power planes is minimized.
6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
AR0230CS/D Rev. 8, Pub. 11/15 EN
8
©Semiconductor Components Industries, LLC, 2015.
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