74HC595DG Datasheet, PDF (8/13 Pages) ON Semiconductor – 8−Bit Serial−Input/Serial or Parallel.Output Shift Register with Latched 3−State Outputs

SHIFT
CLOCK
OUTPUT
SQ_H
t_r
t_f
90%
50%
10%
t_w
90%
50%
10%
1/f_max
t_PLH
t_PHL
t_TLH
t_THL
Figure 1.
LATCH
CLOCK
50%
Q_A−Q_H
90%
50%
OUTPUTS 10%
t_PLH t_PHL
t_TLH
t_THL
Figure 3.
SERIAL
INPUT A
SWITCH
CLOCK
VALID
50%
t_su
t_h
50%
Figure 5.
74HC595
SWITCHING WAVEFORMS
V_CC
GND
V_CC
GND
RESET
OUTPUT
SQ_H
SHIFT
CLOCK
OUTPUT
ENABLE
OUTPUT Q
OUTPUT Q
t_w
V_CC
50%
GND
t_PHL
50%
t_rec
V_CC
50%
GND
Figure 2.
50%
t_PZL
t_PLZ
50%
t_PZH
t_PHZ
50%
Figure 4.
V_CC
GND
HIGH
IMPEDANCE
10% V_OL
90% VOH
HIGH
IMPEDANCE
SHIFT
V_CC
CLOCK
50%
V_CC
GND
GND
t_su
LATCH
V_CC
V_CC
CLOCK
50%
GND
GND
t_w
Figure 6.
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
C_L*
*Includes all probe and jig capacitance
Figure 7.
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
C_L*
CONNECT TO V_CC WHEN
TESTING t_PLZ AND t_PZL.
CONNECT TO GND WHEN
TESTING t_PHZ AND t_PZH.
*Includes all probe and jig capacitance
Figure 8.
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