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74HC595DG Datasheet, PDF (6/13 Pages) ON Semiconductor – 8−Bit Serial−Input/Serial or Parallel.Output Shift Register with Latched 3−State Outputs
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74HC595
TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)
Symbol
Parameter
tsu Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
tsu Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
th
Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
trec Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
tw
Minimum Pulse Width, Reset
(Figure 2)
tw
Minimum Pulse Width, Shift Clock
(Figure 1)
tw
Minimum Pulse Width, Latch Clock
(Figure 6)
tr, tf Maximum Input Rise and Fall Times
(Figure 1)
Guaranteed Limit
VCC
(V) 25_C to –55_C v 85_C v 125_C Unit
2.0
50
3.0
40
4.5
10
6.0
9.0
65
75
ns
50
60
13
15
11
13
2.0
75
3.0
60
4.5
15
6.0
13
95
110
ns
70
80
19
22
16
19
2.0
5.0
3.0
5.0
4.5
5.0
6.0
5.0
5.0
5.0
ns
5.0
5.0
5.0
5.0
5.0
5.0
2.0
50
3.0
40
4.5
10
6.0
9.0
65
75
ns
50
60
13
15
11
13
2.0
60
3.0
45
4.5
12
6.0
10
75
90
ns
60
70
15
18
13
15
2.0
50
3.0
40
4.5
10
6.0
9.0
65
75
ns
50
60
13
15
11
13
2.0
50
3.0
40
4.5
10
6.0
9.0
65
75
ns
50
60
13
15
11
13
2.0
1000
1000
1000
ns
3.0
800
800
800
4.5
500
500
500
6.0
400
400
400
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