74HC595DG Datasheet, PDF (5/13 Pages) ON Semiconductor – 8−Bit Serial−Input/Serial or Parallel.Output Shift Register with Latched 3−State Outputs

74HC595
AC ELECTRICAL CHARACTERISTICS (C_L = 50 pF, Input t_r = t_f = 6.0 ns)
Symbol
Parameter
V_CC
Guaranteed Limit
(V) – 55 to 25_C v 85_C v 125_C Unit
f_max Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
2.0
6.0
3.0
15
4.5
30
6.0
35
4.8
4.0
MHz
10
8.0
24
20
28
24
t_PLH,
t_PHL
Maximum Propagation Delay, Shift Clock to SQ_H
(Figures 1 and 7)
2.0
140
3.0
100
4.5
28
6.0
24
175
210
ns
125
150
35
42
30
36
t_PHL Maximum Propagation Delay, Reset to SQ_H
(Figures 2 and 7)
2.0
145
3.0
100
4.5
29
6.0
25
180
220
ns
125
150
36
44
31
38
t_PLH,
t_PHL
Maximum Propagation Delay, Latch Clock to Q_A − Q_H
(Figures 3 and 7)
2.0
140
3.0
100
4.5
28
6.0
24
175
210
ns
125
150
35
42
30
36
t_PLZ,
t_PHZ
Maximum Propagation Delay, Output Enable to Q_A − Q_H
(Figures 4 and 8)
2.0
150
3.0
100
4.5
30
6.0
26
190
225
ns
125
150
38
45
33
38
t_PZL,
t_PZH
Maximum Propagation Delay, Output Enable to Q_A − Q_H
(Figures 4 and 8)
2.0
135
3.0
90
4.5
27
6.0
23
170
205
ns
110
130
34
41
29
35
t_TLH,
t_THL
Maximum Output Transition Time, Q_A − Q_H
(Figures 3 and 7)
2.0
60
3.0
23
4.5
12
6.0
10
75
90
ns
27
31
15
18
13
15
t_TLH,
t_THL
Maximum Output Transition Time, SQ_H
(Figures 1 and 7)
2.0
75
3.0
27
4.5
15
6.0
13
95
110
ns
32
36
19
22
16
19
C_in Maximum Input Capacitance
−
10
10
10
pF
C_out Maximum Three−State Output Capacitance (Output in
High−Impedance State), Q_A − Q_H
−
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V_CC = 5.0 V
C_PD Power Dissipation Capacitance (Per Package)*
300
pF
* Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
http://onsemi.com
5