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MC74LVX259_14 Datasheet, PDF (7/9 Pages) ON Semiconductor – 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter | |||
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MC74LVX259
ORDERING INFORMATION
Device
Package
Shippingâ
MC74LVX259DG
SOICâ16
(PbâFree)
48 Units / Rail
MC74LVX259DR2G
SOICâ16
(PbâFree)
2500 Tape & Reel
MC74LVX259DTG
TSSOPâ16
(PbâFree)
96 Units / Rail
MC74LVX259DTR2G
TSSOPâ16
(PbâFree)
2500 Tape & Reel
â For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
EMBOSSED CARRIER DIMENSIONS (See Notes 6 and 7)
Tape B1
Size Max
D
D1
E
F
K
P
P0
P2
R
T
W
8 mm 4.35 mm
(0.179â)
12 mm 8.2 mm
(0.323â)
1.5 mm
+ 0.1
â0.0
(0.059â
+0.004
â0.0)
1.0 mm
Min
(0.179â)
1.5 mm
Min
(0.060)
1.75 mm
±0.1
(0.069
±0.004â)
3.5 mm
±0.5
(1.38
±0.002â)
5.5 mm
±0.5
(0.217
±0.002â)
2.4 mm
Max
(0.094â)
6.4 mm
Max
(0.252â)
4.0 mm
±0.10
(0.157
±0.004â)
4.0 mm
±0.10
(0.157
±0.004â)
8.0 mm
±0.10
(0.315
±0.004â)
4.0 mm
±0.1
(0.157
±0.004â)
2.0 mm
±0.1
(0.079
±0.004â)
25 mm
(0.98â)
30 mm
(1.18â)
0.6 mm
(0.024)
8.3 mm
(0.327)
12.0 mm
±0.3
(0.470
±0.012â)
16 mm 12.1 mm
(0.476â)
7.5 mm
±0.10
(0.295
±0.004â)
7.9 mm
Max
(0.311â)
4.0 mm
±0.10
(0.157
±0.004â)
8.0 mm
±0.10
(0.315
±0.004â)
12.0 mm
±0.10
(0.472
±0.004â)
16.3 mm
(0.642)
24 mm 20.1 mm
(0.791â)
11.5 mm
±0.10
(0.453
±0.004â)
11.9 mm
Max
(0.468â)
16.0 mm
±0.10
(0.63
±0.004â)
24.3 mm
(0.957)
6. Metric Dimensions GovernâEnglish are in parentheses for reference only.
7. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
http://onsemi.com
7
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