MC74LVX259_14 Datasheet, PDF (5/9 Pages) ON Semiconductor – 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter

MC74LVX259
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
V_CC
T_A = 25°C
−40°C ≤ T_A ≤ 85°C
(V)
Min Typ Max
Min
Max
Unit
V_IH Minimum High−Level
Input Voltage
V_IL Maximum Low−Level
Input Voltage
V_OH High−Level Output
Voltage
I_OH = −50 mA
I_OH = −50 mA
I_OH = −4 mA
V_OL Low−Level Output
Voltage
I_OL = 50 mA
I_OL = 50 mA
I_OL = 4 mA
I_IN Input Leakage Current V_IN = 5.5 V or GND
I_CC Maximum Quiescent
Supply Current
(per package)
V_IN = V_CC or GND
2.0 0.75 V_CC −
−
0.75 V_CC
−
V
3.0
0.7 V_CC −
−
0.7 V_CC
−
3.6
0.7 V_CC −
−
0.7 V_CC
−
2.0
−
− 0.25 V_CC
−
0.25 V_CC
V
3.0
−
− 0.3 V_CC
−
0.3 V_CC
3.6
−
− 0.3 V_CC
−
0.3 V_CC
2.0
1.9
2.0
−
1.9
−
V
3.0
2.9
3.0
−
2.9
−
3.0
2.58
−
−
2.48
−
2.0
−
0.0
0.1
−
0.1
V
3.0
−
0.0
0.1
−
0.1
3.0
−
−
0.36
−
0.44
0 to 3.6
−
−
±0.1
−
±1.0
mA
3.6
1.0
1.0
2.0
−
−
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS Input t_r = t_f = 3.0 ns
Symbol
Parameter
Test Conditions
T_A = 25°C
−40°C ≤ T_A ≤ 85°C
Min
Typ
Max
Min
Max
Unit
t_PLH, Maximum Propagation V_CC = 2.7 V
C_L = 15pF
−
t_PHL Delay, Data to Output
(Figures 4 and 8)
C_L = 50pF
−
V_CC = 3.3 V ± 0.3 V C_L = 15pF
−
C_L = 50pF
−
6.3
9.0
1.0
9.0
14.0
1.0
5.6
8.0
1.0
8.0
12.0
1.0
12.0
ns
15.0
11.0
14.0
t_PLH, Maximum Propagation V_CC = 2.7 V
C_L = 15pF
−
t_PHL Delay, Address Select
to Output
C_L = 50pF
−
(Figures 5 and 8)
V_CC = 3.3 V ± 0.3 V C_L = 15pF
−
C_L = 50pF
−
6.3
9.0
1.0
9.0
14.0
1.0
5.6
8.0
1.0
8.0
12.0
1.0
12.0
ns
15.0
11.0
14.0
t_PLH,
t_PHL
Maximum Propagation
Delay, Enable to Output
(Figures 6 and 8)
V_CC = 2.7 V
C_L = 15pF
−
C_L = 50pF
−
V_CC = 3.3 V ± 0.3 V C_L = 15pF
−
C_L = 50pF
−
6.3
9.0
1.0
9.0
14.0
1.0
5.6
9.0
1.0
8.0
12.0
1.0
12.0
ns
15.0
11.0
14.0
t_PHL Maximum Propogation V_CC = 2.7 V
C_L = 15pF
−
Delay, Reset to Output
(Figures 6 and 8)
C_L = 50pF
−
V_CC = 3.3 V ± 0.3 V C_L = 15pF
−
C_L = 50pF
−
6.3
9.0
1.0
9.0
14.0
1.0
5.6
9.0
1.0
8.0
12.0
1.0
12.0
ns
15.0
11.0
14.0
C_IN Maximum Input
Capacitance
−
6
10
−
10
pF
Typical @ 25°C, V_CC = 3.3 V
C_PD Power Dissipation Capacitance (Note 5)
30
pF
5. C_PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I_CC(OPR) = C_PD  V_CC  f_in + I_CC. C_PD is used to determine the no−load dynamic
power consumption; P_D = C_PD  V_CC2  f_in + I_CC  V_CC.
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