MC74LVX259_14 Datasheet, PDF (6/9 Pages) ON Semiconductor – 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter

MC74LVX259
TIMING REQUIREMENTS Input t_r = t_f = 3.0 ns
Symbol
t_w
Parameter
Minimum Pulse Width, Reset or Enable
(Figure 7)
t_su
Minimum Setup Time, Address or Data to Enable
(Figure 7)
t_h
Minimum Hold Time, Enable to Address or Data
(Figure 6 or 7)
t_r, t_f Maximum Input, Rise and Fall Times
(Figure 4)
Test Conditions
V_CC = 2.7 V
V_CC = 3.3 V ± 0.3 V
V_CC = 2.7 V
V_CC = 3.3 V ± 0.3 V
V_CC = 2.7 V
V_CC = 3.3 V ± 0.3 V
V_CC = 2.7 V
V_CC = 3.3 V ± 0.3 V
T_A = 25°C
Min Typ Max
4.5
−
−
4.5
−
−
4.0
−
−
3.0
−
−
2.0
−
−
2.0
−
−
−
−
400
−
−
300
T_A = ≤ 85°C
Min Max
5.0
−
5.0
−
4.0
−
3.0
−
2.0
−
2.0
−
−
300
−
300
t_r
DATA
IN
t_PLH
50%
OUTPUT
Q
50%
t_f
V_CC
t_PHL
GND
DATA
IN
ADDRESS
SELECT
50%
50%
t_PHL
OUTPUT
Q
50%
t_PHL
Unit
ns
ns
ns
ns
V_CC
GND
V_CC
GND
V_CC
GND
Figure 4. Switching Waveform
Figure 5. Switching Waveform
DATA IN
ENABLE
OUTPUT Q
t_w
50%
t_PHL
t_w
50%
50%
t_PHL
V_CC
GND
DATA IN
V_CC
RESET
GN-
D
OUTPUT Q
t_w
50%
t_PHL
50%
V_CC
GND
V_CC
GND
Figure 6. Switching Waveform
Figure 7. Switching Waveform
DATA IN OR
ADDRESS
SELECT
50%
ENABLE
t_h(H)
t_su
t_su
50%
Figure 8. Switching Waveform
V_CC
t_h(H)
GND
V_CC
GND
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C_L*
*Includes all probe and jig capacitance
Figure 9. Test Circuit
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