English
Language : 

MC74LVX259_14 Datasheet, PDF (6/9 Pages) ON Semiconductor – 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter
MC74LVX259
TIMING REQUIREMENTS Input tr = tf = 3.0 ns
Symbol
tw
Parameter
Minimum Pulse Width, Reset or Enable
(Figure 7)
tsu
Minimum Setup Time, Address or Data to Enable
(Figure 7)
th
Minimum Hold Time, Enable to Address or Data
(Figure 6 or 7)
tr, tf Maximum Input, Rise and Fall Times
(Figure 4)
Test Conditions
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
VCC = 2.7 V
VCC = 3.3 V ± 0.3 V
TA = 25°C
Min Typ Max
4.5
−
−
4.5
−
−
4.0
−
−
3.0
−
−
2.0
−
−
2.0
−
−
−
−
400
−
−
300
TA = ≤ 85°C
Min Max
5.0
−
5.0
−
4.0
−
3.0
−
2.0
−
2.0
−
−
300
−
300
tr
DATA
IN
tPLH
50%
OUTPUT
Q
50%
tf
VCC
tPHL
GND
DATA
IN
ADDRESS
SELECT
50%
50%
tPHL
OUTPUT
Q
50%
tPHL
Unit
ns
ns
ns
ns
VCC
GND
VCC
GND
VCC
GND
Figure 4. Switching Waveform
Figure 5. Switching Waveform
DATA IN
ENABLE
OUTPUT Q
tw
50%
tPHL
tw
50%
50%
tPHL
VCC
GND
DATA IN
VCC
RESET
GN-
D
OUTPUT Q
tw
50%
tPHL
50%
VCC
GND
VCC
GND
Figure 6. Switching Waveform
Figure 7. Switching Waveform
DATA IN OR
ADDRESS
SELECT
50%
ENABLE
th(H)
tsu
tsu
50%
Figure 8. Switching Waveform
VCC
th(H)
GND
VCC
GND
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
Figure 9. Test Circuit
http://onsemi.com
6