CAT706SZI-GT3 Datasheet, PDF (7/12 Pages) ON Semiconductor – P Supervisory Circuits

CAT705, CAT706, CAT813
WATCHDOG TIMER
The CAT705, CAT706, & CAT813 provide a Watchdog
input (WDI). The watchdog timer function controls the
watchdog output (WDO) signal and forces the WDO to be
low (active) when the WDI input does not have a transition
from low−to−high or high−to−low within 1.6 s typical. If a
transition occurs on the WDI input pin prior to the watchdog
time−out, the watchdog timer is restarted. The timing
diagram is shown in Figure 6. The watchdog timer starts as
soon as reset condition becomes inactive.
When the V_CC supply drops below the reset threshold, the
WDO output becomes active and goes low independently of
the watchdog timing stage.
Figure 7 below shows a typical implementation of a
watchdog function. Any processor signal that repeats
dependant on the normal operation of the processor or
directed by the software operating on the processor can be
used to strobe the watchdog input. The most reliable is a
dedicated I/O output transitioned by a specific software
instruction.
The watchdog can be disabled by floating (or tri−stating)
the WDI input (see Figure 8). If the watchdog is disabled the
WDI pin will be pulled low for the first 7/8^th’s of the
watchdog period (t_WD) and pulled high for the last 1/8^th of
the watchdog period. This pulling low of the WDI input and
then high is used to detect an open or tri−state condition and
will continue to repeat until the WDI input is driven high or
low.
For most efficient operation of devices with the watchdog
function the WDI input should be held low the majority of
the time and only strobed high as required to reset the
watchdog timer.
t_WP
t_WDSU
t_WD
+5 V
WDI
0V
t_WD
t_WD
+5 V
WDO _{0 V}
+5 V
RESET
0V
+5 V
(RESET)
0V
RESET EXTERNALLY
TRIGGERED BY MR
t_RS
(() Are for CAT813 Only)
Figure 6. Watchdog Timing Diagram
MR
WDO
V_CC
GND
PFI
CAT705
CAT706
CAT813
RESET/RESET
WDI
PFO
PIC
mC
MCLR
ADDRESS DECODER
Figure 7. Watchdog Timer Circuit
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