CAT706SZI-GT3 Datasheet, PDF (6/12 Pages) ON Semiconductor – P Supervisory Circuits

CAT705, CAT706, CAT813
TYPICAL PERFORMANCE CHARACTERISTICS
9
1.06
8
1.04
7
1.02
6
5
1.00
4
3
2
1
−40 −20 0
20 40 60 80 100 120
TEMPERATURE (°C)
Figure 2. V_CC Supply Current vs. Temperature
0.98
0.96
0.94
−40 −20
0
20
40
60
80 100
TEMPERATURE (°C)
Figure 3. Normalized Reset Threshold Voltage
vs. Temperature
FUNCTIONAL DESCRIPTION
Processor Reset
The CAT705, CAT706 & CAT813 detect supply voltage
(V_CC) conditions that are below the specified voltage trip
value (V_RST) and provide a reset output to maintain correct
system operation. On power−up, RESET (or RESET for the
CAT813) are kept active for a minimum delay t_RP of 140 ms
after the supply voltage (V_CC) rises above V_RST to allow the
power supply and processor to stabilize. When V_CC drops
below the voltage trip value (V_RST), the reset output signals
RESET (or RESET) are pulled active. RESET (or RESET)
is specifically designed to provide the reset input signals for
processors. This provides reliable and consistent operation
as power is turned on, off or during brownout conditions by
maintaining the processor operation in known conditions.
Manual Reset
The CAT705, CAT706 & CAT813 each have a Manual
Reset (MR) input to allow for alternative control of the reset
outputs. The MR input is designed for direct connection to
a pushbutton (see Figure 4). The MR input is internally
pulled up by 60 kW resistor and must be pulled low to cause
the reset output to go active. Internally, this input is
debounced and timed such that RESET (or RESET) signals
of at least 140 ms minimum will be generated. The min
140 ms t_RP delay commences as the Manual Reset input is
released from the low level. (see Figure 5).
MR
V_CC
CAT705
GND
CAT706
CAT813
PFI
WDO
RESET/RESET
WDI
PFO
Figure 4. Pushbutton RESET
MR
RESET
t_PB
t_PDLY
V_IL
V_IH
t_RP
V_OH
RESET
V_OL
Figure 5. Timing Diagram – Pushbutton RESET
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