CAT5419WI-25 Datasheet, PDF (7/16 Pages) ON Semiconductor – Dual Digitally Programmable Potentiometers with 64 Taps and 2-wire Interface

WRITE OPERATIONS
In the Write mode, the Master device sends the
START condition and the slave address information to
the Slave device. After the Slave generates an
acknowledge, the Master sends the instruction byte
that defines the requested operation of CAT5419. The
instruction byte consist of a four-bit opcode followed
by two register selection bits and two pot selection
bits. After receiving another acknowledge from the
Slave, the Master device transmits the data to be
written into the selected register. The CAT5419
acknowledges once more and the Master generates
the STOP condition, at which time if a nonvolatile data
register is being selected, the device begins an
internal programming cycle to non-volatile memory.
While this internal cycle is in progress, the device will
not respond to any request from the Master device.
Acknowledge Polling
The disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host's write operation, the CAT5419 initiates the
CAT5419
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address. If the CAT5419 is still
busy with the write operation, no ACK will be returned.
If the CAT5419 has completed the write operation, an
ACK will be returned and the host can then proceed
with the next instruction operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the non-volatile
data registers. If the ^{¯W¯P¯} pin is tied to LOW, the data
registers are protected and become read only.
Similarly, ^{¯W¯P¯} pin going LOW after Start will interrupt
non-volatile write to data registers, while ^{¯W¯P¯} pin going
LOW after internal write cycle has started will have no
effect on any write operation. The CAT5419 will
accept both slave addresses and instructions, but the
data registers are protected from programming by the
device’s failure to send an acknowledge after data is
received.
Figure 5. Slave Address Bits
CAT5419 0 1 0 1 A3 A2 A1 A0
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Figure 6. Write Timing
S
T ^{SLAVE/DPP INSTRUCTION}
S
BUS ACTIVITY : ^{A ADDRESS}
BYTE
T
MASTER
R
T
Fixed
Variable
DR1 WCR DATA _{op code}
Data Register Pot/WCR
Address Address
O
P
SDA LINE S
P
A
A
A
C
C
C
K
K
K
2008 SCILLC. All rights reserved.
7
Characteristics subject to change without notice
Doc. No. MD-2115 Rev. I