CAT5419WI-25 Datasheet, PDF (5/16 Pages) ON Semiconductor – Dual Digitally Programmable Potentiometers with 64 Taps and 2-wire Interface

CAT5419
WRITE CYCLES LIMITS
Symbol Parameter
Max Units
t_WR
Write Cycle Time
5 ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
N_END(1)
T_DR(1)
V_ZAP(1)
I_LTH(1)(2)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
Min
Typ
MIL-STD-883, Test Method 1033 1,000,000
MIL-STD-883, Test Method 1008
100
MIL-STD-883, Test Method 3015
2000
JEDEC Standard 17
100
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
Max
Units
Cycles/Byte
Years
Volts
mA
Figure 1. Bus Timing
tF
tHIGH
tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
SDA IN
SDA OUT
tAA
tDH
tSU:STO
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
STOP BIT
5
Doc. No. MD-2115 Rev. I