CAT5251 Datasheet, PDF (7/15 Pages) Catalyst Semiconductor – Quad Digitally Programmable Potentiometer (DPP) with 256 Taps and SPI Interface

INSTRUCTION AND REGISTER
DESCRIPTION
DEVICE TYPE / ADDRESS BYTE
The first byte sent to the CAT5251 from the
master/processor is called the Device Address Byte.
The most significant four bits of the Device Type
address are a device type identifier. These bits for the
CAT5251 are fixed at 0101[B] (refer to Table 1).
The two least significant bits in the slave address
byte, A1 - A0, are the internal slave address and
must match the physical device address which is
defined by the state of the A1 - A0 input pins for the
CAT5251 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A1 - A0 inputs
can be actively driven by CMOS input signals or tied
to V_CC or V_SS. The remaining two bits in the device
address byte must be set to 0.
CAT5251
INSTRUCTION BYTE
The next byte sent to the CAT5251 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I3-I0. The R1 and R0 bits point to one of the
four data registers of each associated potentiometer.
The least two significant bits point to one of four Wiper
Control Registers. The format is shown in Table 2.
Data Register Selection
Data Register Selected R1 R0
DR0
0
0
DR1
0
1
DR2
1
0
DR3
1
1
Table 1. Identification Byte Format
Device Type
Identifier
ID3
ID2
ID1
0
1
0
(MSB)
Table 2. Instruction Byte Format
I3
(MSB)
Instruction
Opcode
I2
I1
ID0
0
1
Slave Address
0
A1
A0
(LSB)
Data Register
Selection
WCR/Pot Selection
I0
R1
R0
P1
P0
(LSB)
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7
Characteristics subject to change without notice
Doc. No. MD-2017 Rev. H