CAT5251 Datasheet, PDF (2/15 Pages) Catalyst Semiconductor – Quad Digitally Programmable Potentiometer (DPP) with 256 Taps and SPI Interface

CAT5251
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to
input all opcodes, byte addresses and data to be
written to the CAT5251. Input data is latched on the
rising edge of the serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5251. During a read
cycle, data is shifted out on the falling edge of the
serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5251. Opcodes, byte
addresses or data present on the SI pin are latched
on the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of four devices
can be addressed on a single bus. A match in the
slave address must be made with the address input
in order to initiate communication with the CAT5251.
R_H, R_L: Resistor End Points
The four sets of R_H and R_L pins are equivalent to the
terminal connections on a mechanical potentiometer.
R_W: Wiper
The four R_W pins are equivalent to the wiper terminal
of a mechanical potentiometer.
¯C¯S¯: _{Chip Select}
¯C¯S¯ _{is the Chip select pin.} ¯C¯S¯ _{low enables the}
CAT5251 and ^{¯C¯S¯} high disables the CAT5251. ^{¯C¯S¯}
high takes the SO output pin to high impedance and
forces the devices into a Standby mode (unless an
internal write operation is underway). The CAT5251
draws ZERO current in the Standby mode. A high to
low transition on ^{¯C¯S¯} is required prior to any
sequence being initiated. A low to high transition on
¯C¯S¯ _{after a valid write sequence is what initiates an}
internal write cycle.
¯W¯P¯: _{Write Protect}
¯W¯P¯ _{is the Write Protect pin. The Write Protect pin}
will allow normal read/write operations when held
high. When ^{¯W¯P¯} is tied low, all non-volatile write
operations to the Data registers are inhibited
(change of wiper control register is allowed). ^{¯W¯P¯}
going low while ^{¯C¯S¯} is still low will interrupt a write to
the registers. If the internal write cycle has already
been initiated, ^{¯W¯P¯} going low will have no effect on
any write operation.
H¯¯O¯L¯D¯: Hold
The ^{¯H¯O¯L¯D¯} pin is used to pause transmission to the
CAT5251 while in the middle of a serial sequence
without having to re-transmit entire sequence at a
later time. To pause, H¯¯O¯L¯D¯ must be brought low
while SCK is low. The SO pin is in a high impedance
state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication, H¯¯O¯L¯D¯ is brought high, while SCK is
low. (H¯¯O¯L¯D¯ should be held high any time this
function is not being used.) H¯¯O¯L¯D¯ may be tied high
directly to V_CC or tied to V_CC through a resistor.
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
SO
A0
R_W3
R_H3
R_L3
NC
V_CC
R_L0
R_H0
R_W0
¯C¯S¯
¯W¯P¯
SI
A1
R_L1
R_H1
R_W1
GND
NC
R_W2
R_H2
R_L2
SCK
H¯¯O¯L¯D¯
Function
Serial Data Output
Device Address, LSB
Wiper Terminal for Potentiometer 3
High Reference Terminal for
Potentiometer 3
Low Reference Terminal for
Potentiometer 3
No Connect
Supply Voltage
Low Reference Terminal for
Potentiometer 0
High Reference Terminal for
Potentiometer 0
Wiper Terminal for Potentiometer 0
Chip Select
Write Protection
Serial Input
Device Address
Low Reference Terminal for
Potentiometer 1
High Reference Terminal for
Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
No Connect
Wiper Terminal for Potentiometer 2
High Reference Terminal for
Potentiometer 2
Low Reference Terminal for
Potentiometer 2
Bus Serial Clock
Hold
Doc. No. MD-2017 Rev. H
2
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice