CAT5251 Datasheet, PDF (1/15 Pages) Catalyst Semiconductor – Quad Digitally Programmable Potentiometer (DPP) with 256 Taps and SPI Interface

CAT5251
Quad Digitally Programmable Potentiometer (DPP™) with
256 Taps and SPI Interface
FEATURES
„ Four linear-taper digitally programmable
potentiometers
„ 254 resistor taps per potentiometer
„ End to end resistance 50 kΩ or 100 kΩ
„ Potentiometer control and memory access via
SPI interface
„ Low wiper resistance, typically 100 Ω
„ Nonvolatile memory storage for up to four
wiper settings for each potentiometer
„ Automatic recall of saved wiper settings at
power up
„ 2.5 to 6.0 volt operation
„ Standby current less than 1 µA
„ 1,000,000 nonvolatile WRITE cycles
„ 100 year nonvolatile memory data retention
„ SOIC 24-lead and TSSOP 24-lead
„ Industrial temperature range
For Ordering Information details, see page 14.
PIN CONFIGURATION
SOIC 24-Lead (W)
TSSOP 24-Lead (Y)
DESCRIPTION
The CAT5251 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of resistive elements connected between
two externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the
wiper tap switches for each DPP. Associated with
each wiper control register are four 8-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
register.
The CAT5251 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40°C to 85°C
industrial operating temperature range and offered in
a 24-lead SOIC and TSSOP package.
FUNCTIONAL DIAGRAM
SO 1
24 H¯¯O¯L¯D¯
A0 2
23 SCK
R_W3 3
22 R_L2
R_H3 4
21 R_H2
R_L3 5
20 R_W2
NC 6 _CAT 19 NC
V_CC 7 ⁵²⁵¹ 18 GND
R_LO 8
17 R_W1
R_HO 9
16 R_H1
R_WO 10
15 R_L1
¯C¯S¯ 11
14 A1
¯W¯P¯ 12
13 SI
CS
SCK
SI
SO
WP
A0
A1
HOLD
SPI BUS
INTERFACE
CONTROL
LOGIC
R_H0 R_H1 R_H2 R_H3
WIPER
CONTROL
REGISTERS
NONVOLATILE
DATA
REGISTERS
R_L0 R_L1 R_L2 R_L3
R_W0
R_W1
R_W2
R_W3
© 2009 SCILLC. All rights reserved.
1
Characteristics subject to change without notice
Doc. No. MD-2017 Rev. H