PACVGA201 Datasheet, PDF (6/8 Pages) California Micro Devices Corp – VGA PORT COMPANION CIRCUIT

Application Information
PACVGA201
Figure 1. Typical Connection Diagram
A resistor may be necessary between the V_CC2 pin and ground if protection against a stream of ESD pulses is
required while the PACVGA201 is in the power-down state. The value of this resistor should be chosen such
that the extra charge deposited into the V_CC2 bypass capacitor by each ESD pulse will be discharged before the
next ESD pulse occurs. The maximum ESD repetition rate specified by the IEC-61000-4-2 standard is one
pulse per second. When the PACVGA201 is in the power-up state, an internal discharge resistor is connected
to ground via a FET switch for this purpose.
For the same reason, V_CC1 and V_CC3 may also require bypass capacitor discharging resistors to ground if there
are no other components in the system to provide a discharge path to ground.
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