PACVGA201 Datasheet, PDF (5/8 Pages) California Micro Devices Corp – VGA PORT COMPANION CIRCUIT

PACVGA201
ELECTRICAL OPERATING CHARACTERISTICS ^{(SEE NOTE 1)}
SYMBOL PARAMETER
I_CC1
V_CC1 Supply Current
I_CC3
V_CC3 Supply Current
V
CC2
V_IH
V_IL
V_OH
V
OL
RR
B, P
I
IN
C_IN
t
PLH
t_PHL
V Pin Open Circuit
CC2
Voltage
Logic High Input Voltage
Logic Low Input Voltage
Logic High Output Voltage
Logic Low Output Voltage
Resistor Value
Input Current
VIDEO_x pins
HSYNC, VSYNC pins
Input Capacitance on
VIDEO_1, VIDEO_2 and
VIDEO_3 pins
SYNC Buffer L => H
Propagation Delay
SYNC Buffer H => L
Propagation Delay
CONDITIONS
MIN
V_CC1 = 5.0V
V_CC3 = 5V; SYNC inputs at GND or V_CC3;
PWR_UP pin at V_CC3; SYNC ouputs unloaded
V_CC3 = 5V; SYNC inputs at 3.0V; PWR_UP
pin at V_CC3; SYNC ouputs unloaded
V = 5V; PWR_UP input at GND; SYNC
CC3
ouputs unloaded
V voltage internally derived from V via
CC2
CC3
diode D1; no external current drawn
V_CC3 = 5V; Note 2
2.0
V_CC3 = 5V; Note 2
I_OH = -4mA, V_CC3 = 5.0V; Note 3
4.4
I = 4mA, V = 5.0V; Note 3
OL
CC3
PWR_UP = V = 5.0V
0.5
CC3
V_CC1 = 5.0V; V_IN = V_CC1 or GND
V = 5.0V; V = V or GND
CC3
IN
CC3
V = 5.0V; V = 2.5V; measured at 1MHz
CC1
IN
V = 2.5V; V = 1.25V; measured at 1MHz
CC1
IN
C = 50pF; V = 5.0V; Input t and t ≤ 5ns
L
CC3
R
F
C_L = 50pF; V_CC3 = 5.0V; Input t_R and t_F ≤ 5ns
TYP MAX UNITS
10
μA
10
μA
200
μA
10
μA
[V -
V
CC3
0.80]
V
0.8
V
V
0.4
V
1
2
MΩ
±1
μA
±1
μA
4
pF
4.5
pF
8
12
ns
8
12
ns
t_R, t_F
SYNC Buffer Output Rise & _{CL = 50pF; VCC3 = 5.0V; Input tR and tF ≤ 5ns}
7.0
ns
Fall Times
V
ESD Withstand Voltage
ESD
V = V = V = 5V; Note 4
CC1
CC2
CC3
±8
kV
Note 1: All parameters specified over standard operating conditions unless otherwise noted.
Note 2: These parameters apply only to SYNC_IN1, SYNC_IN2 and PWR_UP.
Note 3: These parameters apply only to SYNC_OUT1 and SYNC_OUT2.
Note 4: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. V_CC1, V_CC2 and V_CC3 must be
bypassed to GND via a low impedance ground plane with a 0.2uF or greater, low inductance, chip ceramic capacitor at
each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative
with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2,
DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard 2kV per the Human Body
model (MIL-STD-883, Method 3015).
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