PACVGA201 Datasheet, PDF (1/8 Pages) California Micro Devices Corp – VGA PORT COMPANION CIRCUIT

VGA Port Companion Circuit
PACVGA201
Features
• Seven channels of ESD protection for all VGA
port connector pins
• Meets IEC-61000-4-2 Level-4 ESD requirements
(±8kV contact discharge)
• Very low loading capacitance from ESD
protection diodes on VIDEO lines, 4pF typical
• TTL to CMOS level-translating buffers with power
down mode for HSYNC and VSYNC lines
• Three power supplies for design flexibility
• Compact 16-pin QSOP package
• RoHS compliant (lead-free) finishing
Applications
• ESD protection and termination resistors for VGA
(video) port interfaces
• Desktop PCs
• Notebook computers
• LCD monitors
Product Description
The PACVGA201 provides seven channels of ESD
protection for all signal lines commonly found in a
VGA port. ESD protection is implemented with
current-steering diodes designed to safely handle the
high surge currents encountered with IEC-61000-4-2
Level-4 ESD Protection (±8kV contact discharge).
When a channel is subjected to an electrostatic
discharge, the ESD current pulse is diverted via the
protection diodes into the positive supply rail or
ground where it may be safely dissipated.
Separate positive supply rails are provided for the
VIDEO, DDC_OUT and SYNC channels to facilitate
interfacing with low-voltage video controller ICs and
to provide design flexibility in multiple-supply-voltage
environments.
An internal diode (D₁, in schematic below) is provided
such that V_CC2 is derived from V_CC3 (V_CC2 does not
require an external power supply input). In
applications where V_CC3 may be powered down, diode
D₁ blocks any DC current path from the DDC_OUT
pins back to the powered down V_CC3 rail via the upper
ESD protection diodes.
Two non-inverting drivers provide buffering for the
HSYNC and VSYNC signals from the Video
Controller IC (SYNC_IN1, SYNC_IN2). These buffers
accept TTL input levels and convert them to CMOS
output levels that swing between Ground and V_CC3.
When the PWR_UP input is driven LOW, the SYNC
outputs are driven LOW and the SYNC inputs can
float: no current will be drawn from the VCC3 supply.
The PACVGA201 is housed in a 16-pin QSOP
package with RoHS compliant lead-free finishing.
©2010 SCILLC. All rights reserved.
May 2010 Rev. 3
Publication Order Number:
PACVGA201/D