N01S818HA Datasheet, PDF (6/12 Pages) ON Semiconductor – 1 Mb Ultra-Low Power Serial SRAM

N01S818HA
CS
SCK
012345
12 13 14 15 16 17 18 19 20 21
Instruction
24−bit address
Data in
SIO1:0] ^{C3 C2 C1 C0 A11 A10}
MSB
A3 A2 A1 A0 H0 H0 L0 L0 H1 H1
MSB
Notes:
C[3:0] = 02h
H0 = 2 high order bits of data byte 0
L0 = 2 low order bits of data byte 0
H1 = 2 high order bits of data byte 1
L1 = 2 low order bits of data byte 1
Figure 7. DUAL Write Sequence
Ln Ln
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 _{11 12 13}
Instruction
24−bit address
Data in
SIO[3:0] C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2
MSB
MSB
Notes:
C[1:0] = 02h
H0 = 4 high order bits of data byte 0
L0 = 4 low order bits of data byte 0
H1 = 4 high order bits of data byte 1
L1 = 4 low order bits of data byte 1
Figure 8. QUAD Write Sequence
Hn Ln
READ Mode Register (RDMR)
This instruction provides the ability to read the mode
register. The register may be read at any time including
during a Write operation. The Read Mode Register
operation is executed by driving CS low, then sending the
CS
RDMR instruction to the device. Immediately after the
instruction, the device outputs data on the SO (SIO0-3)
pin(s). To complete the operation, drive CS high to terminate
the register read.
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
00000101
Mode Register Data Out
SO
High−Z
76543210
Figure 9. SPI Read Mode Register Sequence (RDMR)
http://onsemi.com
6