N01S818HA Datasheet, PDF (4/12 Pages) ON Semiconductor – 1 Mb Ultra-Low Power Serial SRAM

N01S818HA
CS
SCK _{0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39}
Instruction
24−bit address
SI 0 0 0 0 0 0 1 1 23 22 21 20 2 1 0
Don’t Care
ADDR 1
Data Out from ADDR 1
SO
High−Z
76543210
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Don’t Care
Data Out from ADDR 2
Data Out from ADDR 3
Data Out from ADDR n
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ... 7 6 5 4 3 2 1 0
Figure 3. SPI Read Sequence (Sequential Bytes)
CS
SCK
012345
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Instruction
24−bit address
Data out
SIO[1:0]
C3 C2 C1 C0 A11 A10
MSB
A3 A2 A1 A0 X X X X H0 H0 L0 L0 H1 H1 L1 L1
MSB
Notes:
C[3:0] = 03h
H0 = 2 high order bits of data byte 0
L0 = 2 low order bits of data byte 0
H1 = 2 high order bits of data byte 1
L1 = 2 low order bits of data byte 1
Figure 4. DUAL Read Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Instruction
24−bit address
Data out
SIO[3:0] C1 C0 A5 A4 A3 A2 A1 A0 X X H0 L0 H1 L1 H2 L2 H3 L3
MSB
MSB
Notes:
C[1:0] = 03h
H0 = 4 high order bits of data byte 0
L0 = 4 low order bits of data byte 0
H1 = 4 high order bits of data byte 1
L1 = 4 low order bits of data byte 1
Figure 5. QUAD Read Sequence
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