MC10E116_16 Datasheet, PDF (6/8 Pages) ON Semiconductor – 5V ECL Quint Differential Line Receiver

MC10E116, MC100E116
Table 7. AC CHARACTERISTICS (V_CCx= 5.0 V; V_EE = 0.0 V or V_CCx = 0.0 V; V_EE = −5.0 V (Note 1))
−40°C
25°C
85°C
Symbol
f_MAX
t_PLH
t_PHL
Characteristic
Maximum Toggle Frequency
Propagation Delay to Output
D (Differential Configuration)
D (Single-Ended)
Min Typ Max Min Typ Max Min Typ Max _Unit
800
800
800
MHz
ps
150 300 500 200 300 450 200 300 450
150 300 550 150 300 500 150 300 500
t_skew Within-Device Skew (Note 2)
50
t_skew Duty Cycle Skew (Note 3) t_PLH − t_PHL
±10
t_JITTER Random Clock Jitter (RMS)
<1
V_PP Input Voltage Swing
150
(Differential Configuration)
50
±10
<1
150
50
ps
±10
ps
<1
ps
150
mV
t_r/t_f Rise/Fall Time 20−80%
250 375 625 275 375 575 275 375 575 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. 10 Series: V_EE can vary −0.46 V / +0.06 V.
100 Series: V_EE can vary −0.46 V / +0.8 V.
2. Within-device skew is defined as identical transitions on similar paths through a device.
3. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point
of the outputs.
Q
Driver
Device
Q
Z_o = 50 W
Z_o = 50 W
50 W
50 W
D
Receiver
Device
D
V_TT
V_TT = V_CC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices)
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
www.onsemi.com
6