CAT5269_13 Datasheet, PDF (6/15 Pages) ON Semiconductor – Dual Digital Potentiometer (POT)

CAT5269
Table 8. POWER UP TIMING (Notes 9, 10)
Symbol
t_PUR
t_PUW
Power-up to Read Operation
Power-up to Write Operation
Parameter
Max
Units
1
ms
1
ms
Table 9. WIPER TIMING
Symbol
Parameter
t_WRPO
t_WRL
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
Max
Units
10
ms
10
ms
Table 10. WRITE CYCLE LIMITS (Note 11)
Symbol
t_WR
Write Cycle Time
Parameter
Max
Units
5
ms
Table 11. RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
N_END (Note 9)
Endurance
MIL−STD−883, Test Method 1033
1,000,000
Cycles/Byte
T_DR (Note 9)
Data Retention
MIL−STD−883, Test Method 1008
100
Years
V_ZAP (Note 9)
ESD Susceptibility
MIL−STD−883, Test Method 3015
2000
V
I_LTH (Note 9)
Latch-up
JEDEC Standard 17
100
mA
9. This parameter is tested initially and after a design or process change that affects the parameter.
10. t_PUR and t_PUW are delays required from the time V_CC is stable until the specified operation can be initiated.
11. The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
t_F
SCL
t_SU:STA
SDA IN
SDA OUT
t_HIGH
t_R
t_LOW
t_LOW
t_HD:STA
t_HD:DAT
t_SU:DAT
t_AA
t_DH
Figure 2. Bus Timing
t_SU:STO
t_BUF
http://onsemi.com
6