CAT5269_13 Datasheet, PDF (4/15 Pages) ON Semiconductor – Dual Digital Potentiometer (POT)

CAT5269
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Temperature Under Bias
−55 to +125
C
Storage Temperature
−65 to +150
C
Voltage on Any Pin with Respect to V_SS (Note 1)
V_CC with Respect to Ground
Package Power Dissipation Capability (T_A = 25C)
Lead Soldering Temperature (10 s)
−2.0 to +V_CC + 2.0
V
−2.0 to +7.0
V
1.0
W
300
C
Wiper Current
6
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameters
V_CC
Industrial Temperature
Ratings
+2.5 to +6.0
−40 to +85
Units
V
C
Table 4. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
R_POT
R_POT
Potentiometer Resistance (100 kW)
Potentiometer Resistance (50 kW)
Potentiometer Resistance Tolerance
100
kW
50
kW
20
%
R_POT Matching
Power Rating
25C, each pot
1
%
50
mW
I_W
R_W
R_W
V_TERM
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R_H or R_L Pin
Resolution
3
mA
I_W = 3 mA @ V_CC = 3 V
I_W = 3 mA @ V_CC = 5 V
200
300
W
100
150
W
V_SS = 0 V
V_SS
V_CC
V
0.4
%
Absolute Linearity (Note 4)
R_w(n)(actual)−R_{(n)(expected)}
(Note 7)
1
LSB
(Note 6)
Relative Linearity (Note 5)
R_w(n+1)−[R_w(n)+LSB]
(Note 7)
0.2
LSB
(Note 6)
TC_RPOT
Temperature Coefficient of R_POT
(Note 3)
300
ppm/C
TC_RATIO
Ratiometric Temp. Coefficient
(Note 3)
20
ppm/C
C_H/C_L/C_W Potentiometer Capacitances
(Note 3)
10/10/25
pF
fc
Frequency Response
R_POT = 50 kW (Note 3)
0.4
MHz
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V_CC +0.5 V, which may overshoot to V_CC +2.0 V for periods of less than 20 ns.
2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V_CC +1 V.
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
5. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
It is a measure of the error in step size.
6. LSB = R_TOT / 255 or (R_H − R_L) / 255, single pot
7. n = 0, 1, 2, ..., 255
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