CAT28F020 Datasheet, PDF (6/16 Pages) Catalyst Semiconductor – 2 Megabit CMOS Flash Memory

CAT28F020
A.C. CHARACTERISTICS, Program/Erase Operation
V_CC = +5V ±10%, unless otherwise specified. (See Note 6)
JEDEC Standard
Symbol Symbol
t_AVAV
t_WC
t_AVWL
t_AS
t_WLAX
t_AH
t_DVWH
t_DS
t_WHDX
t_DH
t_ELWL
t_CS
t_WHEH
t_CH
t_WLWH
t_WP
t_WHWL
t_WPH
t_WHWH1(2)
-
t_WHWH2(2)
-
t_WHGL
-
t_GHWL
-
t_VPEL
-
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
CE Setup Time
CE Hold Time
WE Pulse Width
WE High Pulse Width
Program Pulse Width
Erase Pulse Width
Write Recovery Time Before Read
Read Recovery Time Before Write
V_PP Setup Time to CE
28F020-90
28F020-12
Min Typ Max Min Typ Max
90
120
0
0
40
40
40
40
10
10
0
0
0
0
40
40
20
20
10
10
9.5
9.5
6
6
0
0
100
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
µs
µs
ns
ERASE AND PROGRAMMING PERFORMANCE⁽¹⁾
28F020-90
28F020-12
Parameter
Min Typ Max Min Typ
Max
Unit
Chip Erase Time⁽³⁾⁽⁵⁾
0.5
10
0.5
10
sec
Chip Program Time⁽³⁾⁽⁴⁾
4
25
4
25
sec
Note:
1. Please refer to Supply characteristics for the value of V_PPH and V_PPL. The V_PP supply can be either hardwired or switched. If V_PP is switched,
V_PPL can be ground, less than V_CC + 2.0V or a no connect with a resistor tied to ground.
2. Program and Erase operations are controlled by internal stop timers.
3. ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V V_PP.
4. Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/
byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since
most bytes program significantly faster than the worst case byte.
5. Excludes 00H Programming prior to Erasure.
6. CAT28F020-90, V_CCMIN = 4.75 V
Doc. No. MD-1029, Rev. F
6
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Characteristics subject to change without notice