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CAT28F020 Datasheet, PDF (3/16 Pages) Catalyst Semiconductor – 2 Megabit CMOS Flash Memory
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CAT28F020
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –45°C to +130°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
Voltage on Pin A9 with
Respect to Ground(1) ................... –2.0V to +13.5V
VPP with Respect to Ground
during Program/Erase(1) .............. –2.0V to +14.0V
VCC with Respect to Ground(1) ............ –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Test Method
Min
Typ Max
Units
NEND(3)
Endurance
MIL-STD-883, Test Method 1033 100K
Cycles/Byte
TDR(3)
Data Retention MIL-STD-883, Test Method 1008 10
Years
VZAP(3)
ESD Susceptibility MIL-STD-883, Test Method 3015 2000
Volts
ILTH(3)(4)
Latch-Up
JEDEC Standard 17
100
mA
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol
Test
CIN(3)
Input Pin Capacitance
COUT(3)
Output Pin Capacitance
CVPP(3)
VPP Supply Capacitance
Conditions
VIN = 0V
VOUT = 0V
VPP = 0V
Min
Typ Max
Units
6
pF
10
pF
25
pF
Note:
1. The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-1029, Rev. F
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