CAT25128LI-G Datasheet, PDF (6/20 Pages) ON Semiconductor – 128-Kb SPI Serial CMOS EEPROM

CAT25128
Pin Description
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT25128.
CS: The chip select input pin is used to enable/disable the
CAT25128. When CS is high, the SO output is tri−stated (high
impedance) and the device is in Standby Mode (unless an
internal write operation is in progress). Every communication
session between host and CAT25128 must be preceded by a
high to low transition and concluded with a low to high
transition of the CS input.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
HOLD: The HOLD input pin is used to pause transmission
between host and CAT25128, without having to retransmit
the entire sequence at a later time. To pause, HOLD must be
taken low and to resume it must be taken back high, with the
SCK input low during both transitions. When not used for
pausing, it is recommended the HOLD input to be tied to
V_CC, either directly or through a resistor.
Functional Description
The CAT25128 device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 10.
Reading data stored in the CAT25128 is accomplished by
simply providing the READ command and an address.
Writing to the CAT25128, in addition to a WRITE
command, address and data, also requires enabling the
device for writing by first setting certain bits in a Status
Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAT25128 will accept any one of the six instruction
op−codes listed in Table 10 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
The CAT25128, New Product Rev E features an
additional Identification Page (64 bytes) which can be
accessed for Read and Write operations when the IPL bit
from the Status Register is set to “1”. The user can also
choose to make the Identification Page permanent write
protected.
Table 10. INSTRUCTION SET
Instruction
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory
WRITE
0000 0010
Write Data to Memory
t_CS
CS
t_CNH
SCK
SI
HI−Z
SO
t_CSS
t_WH
t_WL
t_CSH
t_H
t_SU
VALID
IN
t_RI
t_FI
t_V
t_V
t_HO
VALID
OUT
Figure 2. Synchronous Data Timing
t_CNS
t_DIS
HI−Z
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