AND8066 Datasheet, PDF (6/8 Pages) ON Semiconductor – Interfacing with ECLinPS

AND8066/D
When a 100 Series device drives a 10 Series device,
single–ended, the noise margins are very robust and immunity
is optimized (See Table 3).
Table 3. Noise Margins: MC100EP16DT Interfaced to
an MC10EP16DT Receiver
100 to 10 Noise
Margin HIGH
Temp.
–40°C
V_OH(min) – V_IH(min)
2405 – 2090
Delta
(mV)
315
25°C
2405 – 2155
250
85°C
2405 – 2215
190
100 to 10 Noise
Margin LOW
Temp.
–40 °C
25°C
85°C
V_OL(max) – V_IL(max)
1605 – 1690
1605 – 1755
1605 – 1810
Delta
(mV)
–85
–150
–205
Edge Rates (dV/dT)
As a driver rising edge approaches the transfer voltage
point of the receiver input, the receiver diminishes in voltage
according to the small signal gain of the device. When the
input voltage level passes through the transfer crosspoint, the
output will “switch” states in an analog or operational
amplifier mode. Non–signal voltage fluctuations and noise
will be amplified. These phenomena will determine the
suitable edge rate limitation. As the edge becomes slower,
ambient noise present on the input pin will typically constrain
practical usability. Typically, this may be from 5 ns to 35 ns
and further precaution, such as shielding, will extend the
operating edge times.
For signal edges slower than 20 ns, a Schmitt trigger circuit
may be considered to reliably sharpen the edge rates. In
theory, ECL logic may operate from sub–hertz (< 1.0 Hz)
frequencies, but real circuit conditions will constrain practical
limits.
D_IN
16
R2 ^VBB
400 W
RT RT
Q_out
Q_out
R1
1 kW
V_TT
0.01 mF
V_CC or V_TT
Figure 18. Schmitt Trigger with 228 mV Hysteresis
Schmitt conditioning may be determined by the resistor
values. An R1 resistor of 1 kW provides inverted output
feedback resistor (R_fb) from Qout to the threshold voltage
point, D. A 400 W bias resistor, R2, to V_BB sets the voltage
offset as a fraction of the output voltage from V_BB. With an
800 mV V_out swing, V_BB will be the midpoint between V_OH
and V_OL, or 400 mV from a state level. The two resistors
form a voltage divider from either state level to V_BB.About
28% of the LOW or HIGH state level is developed at the
voltage divider node and ported to D. This will be the offset
a signal must exceed to force the buffer to switch states.
For
tr
Voffset
+
R1
R2
) R2
<
(
VOL
*
VBB
)
+
400
1400
<
400
+ 114mV
For
tf
Voffset
+
R1
R2
)
R2
<
(
VOH
*
VBB
)
+
400
1400
<
400
+ 114mV
This creates a total of 228 mV of hysteresis conditioning.
The effect of the hysteresis delay in a signal must be
considered in the timing analysis.
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