AND8066 Datasheet, PDF (3/8 Pages) ON Semiconductor – Interfacing with ECLinPS

AND8066/D
Depending on system requirements, V_BB may be
generated by a dedicated supply, a “16” type buffer, or by
using a bypassed resistor voltage divider.
Dedicated Single–Ended Input Structure
A device may have a dedicated single–ended input, having
only one of the internal differential base inputs pinned out of the
package, available to be driven by a signal. Internal circuitry
connects a V_BB voltage reference to the other internal,
non–driven input base node of the differential buffer gate, as
shown in Figure 2. This internal, fixed reference voltage, V_BB,
is maintained at the midpoint between V_IL and V_IH for
dedicated single–ended inputs. The internal V_BB is derived from
referencing the V_CC supply and tracks changes 1:1 in this
supply. Noise and drift in V_CC will inject jitter and phase noise
directly into the signal.
DIFFERENTIAL INTERFACE
A standard differential interconnect driver signal will be
received as signal swing. Historically, standard ECL driver
signal swing may range from 750 mV to 1040 mV depending
on the family, although 800 mV is typical. Newer devices may
offer RSECL (Reduced Swing ECL) or Variable Output Swing
(NBSG16VS). Receiver sensitivity is specified by data sheets as
the input swing voltage peak–to–peak (V_pp). Proper output
operation is displayed as the typical amplitude through the entire
range of input swing, from minimum to maximum as shown in
Figure 9: V_pp – Input Swing Voltage Peak–to–Peak. Input
swings greater than specification limit maximum may cause
degraded frequency performance and increased t_pd input. Input
swings less than specification minimum will cause diminished
output amplitude due to the device voltage gain and low enough
input amplitude will result in a loss of output signal. All
waveforms are measured with single ended probes with
reference to ground (not as a differential probe value). Operation
in the small signal level range less than V_pp minimum display
a characteristic gain and may obviously be operated as a limited
linear amplifier this input swing range.
Max
Min
Typ
Input V_pp
Output V_pp
Figure 9. V_pp – Input Swing Voltage Peak–to–Peak
Noise common to both differential lines and within the input
operating range will be rejected and ignored by the receiver.
The transfer threshold point is determined by the crosspoint of
the differential signal. A voltage shift in input operating range
of the transfer point has no voltage or timing effect on the
signal, therefore, preserving integrity. A receiver’s tolerance of
common mode interference is illustrated in Figure 10.
t₁
t₂
Input
t₁
t₂
Output
Figure 10. Differential Input High Noise Immunity
V_IHCMR
Each input signal to a differential pair receiver will display a
Vin HIGH voltage (V_IH) level and a Vin LOW voltage V_IL.
Proper operation is achieved when the Vin HIGH voltage (V_IH)
level falls within spec limits, V_IHCMR (Voltage Input High
Common Mode Range) minimum to maximum as represented
in Figure 11.
V_IHCMR
V_IH(max)
V_IN(pp)
V_IH(min)
t₁ t₂ t₃ t₄
Input
V_OUT(pp)
t₁ t₂ t₃ t₄
Output
Figure 11. V_IH Common Mode Range, V_IHCMR
Considerations for Single–Ended and Differential
Interconnects
Several advantages and disadvantages are listed below.
Single–Ended (SE) Interconnects
Advantages may include:
• Decreased board real estate routing.
• Reduced system power demand.
Disadvantages may include:
• Higher jitter, phase error, and duty cycle skew.
• High noise sensitivity.
• Critically narrow interface windows.
• Poor receiver sensitivity.
• Higher EMI emission.
Differential Interconnects
Advantages may include:
• High common mode noise rejection (low noise
sensitivity).
http://onsemi.com
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