AND8066 Datasheet, PDF (1/8 Pages) ON Semiconductor – Interfacing with ECLinPS

AND8066/D
Interfacing with ECLinPS
Prepared by: Paul Shockman
ON Semiconductor Logic Applications Engineering
STANDARD ECL INTERFACE: DIFFERENTIAL
DRIVER AND RECEIVER
A typical Emitter Coupled Logic (ECL) circuit interface
may be defined as a differential driver device sending a paired
set of commentary signals – True and Invert – over a pair of
standard, controlled impedance lines to an ECL differential
receiver device. A typical ECL output line driver consists of
a bipolar transistor in an Emitter Follower configuration with
the collector at V_CC power supply rail and the emitter pinned
out. A standard, typical differential ECL receiver consists of
a pair of bipolar transistors in a differential configuration with
the True and Invert signals providing base drives to the two
base inputs. Proper differential levels are specified as V_pp and
V_IHCMR. When an input is interconnected as a differential
signal, the DC Single Ended parameters of V_IL and V_IH do not
apply. Terminations are required to preserve optimum signal
integrity, as shown in Figure 1. The standard, controlled
impedance lines assume a sufficient return current capability.
V_CC
Q
True
V_CC
D
Q
Q
V_EE
Invert
D
Q
V_EE
V_TT
Figure 1. Standard Differential ECL Interconnect
SINGLE–ENDED INTERFACE
Signals may be imported as full differential lines or as a
Single–Ended (SE) line interconnection. The SE
interconnection may be seen as a special variation of the
typical differential interface using only one driver source
trace line. This single trace line drives a (Base) input pin of
the receiver, as shown in Figure 2. Although a receiver may
present only a single, dedicate SE input pin instead of a
differential input pair of pins, such a receiver still would have
a differential structure with the unavailable input controlled
by internal circuitry.
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APPLICATION NOTE
V_CC
V_CC
True
V_EE
V_EE
V_TT
Figure 2. Standard Single–Ended ECL Interconnect
Single–ended receiver input levels are specified in data
sheets DC CHARACTERISTICS block as V_IH and V_IL
Parameters. Each temperature has a minimum and
maximum limit pair to V_IH and V_IL parameters, thus
defining the Single–Ended input swing, V_pp(SE). The
V_pp(SE) ranges from 595 mV to 890 mV, depending on the
temperature and family. The V_pp(SE) limits constitute the
receiver device’s input single–ended sensitivity.
Both output lines of the typical differential output may
drive two independent single–ended receivers separately (see
Figure 3).
V_CC
V_CC
Q
Q
V_EE
True
Invert
Q
V_EE
V_TT
V_CC
Q
V_TT
V_EE
Figure 3. Differential Driver with Independent
Standard Single–Ended Receivers
© Semiconductor Components Industries, LLC, 2002
1
May, 2002 – Rev. 2
Publication Order Number:
AND8066/D