AMIS-42700 Datasheet, PDF (6/14 Pages) AMI SEMICONDUCTOR – Dual High-Speed CAN Transceiver

AMIS−42700
Table 3. Function of the Logic Unit (bold letters describe input signals)
EN1B
EN2B
TX0
TEXT
Bus 1 State
Bus 2 State
RX0
0
1
1
1
recessive
dominant (Note 3)
1
1
0
0
0
recessive
dominant
0
1
0
0
1
recessive
dominant
0
1
0
1
0
recessive
dominant
0
1
0
1
1
recessive
recessive
1
1
0
1
1
dominant (Note 3)
recessive
1
1
0
1
1
recessive
dominant (Note 3)
0
1
1
0
0
recessive
recessive
0
1
1
0
1
recessive
recessive
0
1
1
1
0
recessive
recessive
0
1
1
1
1
recessive
recessive
1
1
1
1
1
dominant (Note 3)
recessive
1
1
1
1
1
recessive
dominant (Note 3)
1
3. Dominant detected by the corresponding receiver.
RINT
1
0
0
1
1
1
0
0
0
1
1
1
1
Receivers
Two bus receiving sections sense the states of the bus
lines. Each receiver section consists of an input filter and a
fast and accurate comparator. The aim of the input filter is
to improve the immunity against high−frequency
disturbances and also to convert the voltage at the bus lines
CANHx and CANLx, which can vary from –12 V to +12 V,
to voltages in the range 0 to 5 V, which can be applied to the
comparators.
The output signal of the comparators is gated by the ENBx
signal. In the disabled state (ENBX = high), the output signal
of the comparator will be replaced by a permanently
recessive state and does not depend on the bus voltage. In the
enabled state the receiver signal sent to the logic unit is
identical to the comparator output signal.
Time−out Counters
To avoid that the transceiver drives a permanent dominant
state on either of the bus lines (blocking all communication),
time−out function is implemented. Signals on pins Tx0 and
Text as well as both bus receivers are connected to the logic
unit through independent timers. If the input of the timer
stays dominant for longer than parameter tdom, it’s replaced
by a recessive signal on the timer output.
Feedback Suppression
The logic unit described in Table 3 constantly ensures that
dominant symbols on one bus line are transmitted to the
other bus line without imposing any priority on either of the
lines. This feature would lead to an “interlock” state with
permanent dominant signal transmitted to both bus lines, if
no extra measure is taken.
Therefore a feedback suppression is included inside the
logic unit of the transceiver. This block masks−out reception
on that bus line, on which a dominant is actively transmitted.
The reception becomes active again only with certain delay
after the dominant transmission on this line is finished.
Power−on−Reset (POR)
While Vcc voltage is below the POR level, the POR
circuit makes sure that:
• The counters are kept in the reset mode and stable state
without current consumption
• Inputs are disabled (don’t care)
• Outputs are high impedant; only Rx0 = high−level
• Analog blocks are in power down
• Oscillator not running and in power down
• CANHx and CANLx are recessive
• VREF output high impedant for POR not released
Over Temperature Detection
A thermal protection circuit is integrated to prevent the
transceiver from damage if the junction temperature
exceeds thermal shutdown level. Because the transmitters
dissipate most of the total power, the transmitters will be
switched off only to reduce power dissipation and IC
temperature. All other IC functions continue to operate.
Fault Behavior
A fault like a short circuit is limited to that bus line where
it occurs; hence data interchange from the protocol IC to the
other bus system is not affected.
When the voltage at the bus lines is going out of the normal
operating range (−12 V to +12 V), the receiver is not allowed
to erroneously detect a dominant state.
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