AMIS-42700 Datasheet, PDF (5/14 Pages) AMI SEMICONDUCTOR – Dual High-Speed CAN Transceiver

AMIS−42700
Functional Description
Overall Functional Description
AMIS−42700 is specially designed to provide the link
between the protocol IC (CAN controller) and two physical
bus lines. Data interchange between those two bus lines is
realized via the logic unit inside the chip. To provide an
independent switch−off of the transceiver units for both bus
systems by a third device (e.g. the mC), enable−inputs for the
corresponding driving and receiving sections are provided.
As long as both lines are enabled, they appear as one logical
bus to all nodes connected to either of them.
The bus lines can have two logical states, dominant or
recessive. A bus is in the recessive state when the driving
sections of all transceivers connected to the bus are passive.
The differential voltage between the two wires is
approximately zero. If at least one driver is active, the bus
changes into the dominant state. This state is represented by
a differential voltage greater than a minimum threshold and
therefore by a current flow through the terminating resistors
of the bus line. The recessive state is overwritten by the
dominant state.
In case of a fault (like short circuit) is present on one of the
bus lines, it remains limited to that bus line where it occurs.
Data interchange from the protocol IC to the other bus
system and on this bus system itself can be continued.
AMIS−42700 can be also used for only one bus system. If
the connections for the second bus system are simply left
open it serves as a single transceiver for an electronic unit.
For correct operation, it is necessary to terminate the open
bus by the proper termination resistor.
Logic Unit and CAN Controller Interface
The logic unit inside AMIS−42700 provides data transfer
from/to the digital interface to/from the two busses and from
one bus to the other bus. The detailed function of the logic
unit is described in Table 3.
All digital input pins, including ENBx, have an internal
pull-up resistor to ensure a recessive state when the input is
not connected or is accidentally interrupted. A dominant
state on the bus line is represented by a low-level at the
digital interface; a recessive state is represented by a
high-level.
Dominant state received on any bus (if enabled) causes a
dominant state on both busses, pin Rint and pin Rx0.
Dominant signal on any of the input pins Tx0 and Text
causes transmission of dominant on both bus lines (if
enabled).
Digital inputs Tx0 and Text are used for connecting the
internal logic’s of several IC’s to obtain versions with more
than two bus outputs (see Figure 4: Application Diagram
CAN-bus Extender). They have also a direct logical link to
pins Rx0 and Rint independently on the EN1x pins −
dominant on Tx0 is directly transferred to both Rx0 and Rint
pins, dominant on Text is only transferred to Rx0.
Transmitters
The transceiver includes two transmitters, one for each
bus line, and a driver control circuit. Each transmitter is
implemented as a push and a pull driver. The drivers will be
active if the transmission of a dominant bit is required.
During the transmission of a recessive bit all drivers are
passive. The transmitters have a built−in current limiting
circuit that protects the driver stages from damage caused by
accidental short circuit to either positive supply voltage or
to ground. Additionally a thermal protection circuit is
integrated.
The driver control circuit ensures that the drivers are
switched on and off with a controlled slope to limit EME.
The driver control circuit will be controlled itself by the
thermal protection circuit, the timer circuit and the logic
unit.
The enable signal ENBx allows the transmitter to be
switched off by a third device (e.g. the mC). In the disabled
state (ENBx = high) the corresponding transmitter behaves
as in the recessive state.
Table 3. Function of the Logic Unit (bold letters describe input signals)
EN1B
EN2B
TX0
TEXT
Bus 1 State
Bus 2 State
RX0
0
0
0
0
dominant
dominant
0
0
0
0
1
dominant
dominant
0
0
0
1
0
dominant
dominant
0
0
0
1
1
recessive
recessive
1
0
0
1
1
dominant (Note 3)
dominant
0
0
0
1
1
dominant
dominant (Note 3)
0
0
1
0
0
dominant
recessive
0
0
1
0
1
dominant
recessive
0
0
1
1
0
dominant
recessive
0
0
1
1
1
recessive
recessive
1
0
1
1
1
dominant (Note 3)
recessive
0
3. Dominant detected by the corresponding receiver.
RINT
0
0
1
1
0
0
0
0
1
1
0
http://onsemi.com
5