AMIS-30624_13 Datasheet, PDF (41/52 Pages) ON Semiconductor – I2C Micro-stepping Motor Driver

AMIS−30624, NCV70624
S Slave Address R/W A Internal Address A P
”0” = WRITE
Figure 29. Master Reading Data from AMIS−30624/NCV70624: First Transmission is Addressing
2. The second transmission consists of the slave
address and the read bit. Then the master can read
the data bits on the SDA line on every rising edge
of signal SCK. After each byte of data the master
has to acknowledge correct data reception by
pulling SDA LOW. The last byte is not
acknowledged by the master and therefore the
slave knows the end of transmission.
S Slave Address R/W A
Data
A
Data
AP
”0” = WRITE
N bytes + Acknowledge
Master to AMIS−30624
AMIS−30624 to Master
S = Start condition
P = Stop condition
A = Acknowledge (SDA = LOW)
A = No Acknowledge (SDA = HIGH)
Figure 30. Master Reading Data from AMIS−30624/NCV70624: Second Transmission is Reading Data
Notes:
1. Each byte is followed by an acknowledgment bit as indicated by the A or A in the sequence.
2. I²C−bus compatible devices must reset their bus logic on receipt of a START condition such that they all anticipate the sending of a
slave address, even if these START conditions are not positioned according to the proper format.
3. A START condition immediately followed by a STOP condition (void message) is an illegal format.
7−bit Addressing
The addressing procedure for the I²C−bus is such that the
first byte after the START condition usually determines
which slave will be selected by the master. The exception is
the general call address which can call all devices. When this
address is used all devices should respond with an
acknowledge. The second byte of the general call address
then defines the action to be taken.
Definition of Bits in the First Byte
The first seven bits of the first byte make up the slave
address. The eighth bit is the least significant bit (LSB). It
determines the direction of the message. If the LSB is a
“zero” it means that the master will write information to a
selected slave. A “one” in this position means that the master
will read information from the slave. When an address is
sent, each device in a system compares the first seven bits
after the START condition with its address. If they match,
the device considers itself addressed by the master as a
slave−receiver or slave−transmitter, depending on the R/W
bit.
AMIS−30624/NCV70624 is provided with a physical
address in order to discriminate this circuit from other
circuits on the I²C bus. This address is coded on seven bits
(two bits being internally hardwired to ‘1’), yielding the
theoretical possibility of 32 different circuits on the same
bus. It is a combination of four OTP memory bits (OTP
Memory Structure OPEN) and of the externally hardwired
address bits (pin HW). HW must either be connected to
ground or to V_bat. When HW is not connected and is left
floating, correct functionality of the positioner is not
guaranteed. The motor will be driven to the programmed
secure position (See Hardwired Address – OPEN).
MSB
LSB
1 1 PA3 PA2 PA1 PA0 HW R/W
OTP memory Hardwired Address Bit
Figure 32. First Byte after START Procedure
MSB
LSB
R/W
SLAVE ADDRESS
Figure 31. First Byte after START Procedure
General Call Address
The AMIS−30624/NCV70624 supports also a “general
call” address “000 0000”, which can address all devices.
When this address is used all devices should respond with an
acknowledge. The second byte of the general call address
then defines the action to be taken.
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