AMIS-30624_13 Datasheet, PDF (22/52 Pages) ON Semiconductor – I2C Micro-stepping Motor Driver

DriveHS
AMIS−30624, NCV70624
Tsw = 1024 ms
512 ms
t
Tsw_on = 128 ms
DriveLS
t
“R”−Comp
R_th
t
SWI_Cmp
120 ms
t
ESW
0
1
1
1
t
ActPos
t
Figure 13. Simplified Timing Diagram Showing the Change in States for SWI Comparator
Main Control and Register, OTP memory + ROM
Power−up Phase
Power−up phase of the AMIS−30624/NCV70624 will not
exceed 10 ms. After this phase, the
AMIS−30624/NCV70624 is in standby mode, ready to
receive I²C messages and execute the associated commands.
After power−up, the registers and flags are in the reset state,
while some of them are being loaded with the OTP memory
content (see Table 19: RAM Registers).
Reset
After power−up, or after a reset occurrence (e.g. a
micro−cut on pin V_BB has made V_DD to go below VddReset
level), the H−bridges will be in high−impedance mode, and
the registers and flags will be in a predetermined position.
This is documented in Table 19: RAM Registers and
Table 20: Flags Table.
Soft−stop
A soft−stop is an immediate interruption of a motion, but
with a deceleration phase. At the end of this action, the
register <TagPos> is loaded with the value contained in
register <ActPos>, see Table 19: Ram Registers). The
circuit is then ready to execute a new positioning command,
provided thermal and electrical conditions allow for it.
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