NSL12AW Datasheet, PDF (4/4 Pages) ON Semiconductor – High Current Surface Mount PNP Silicon Low VCE(sat) Transistor for Battery Operated Applications

NSL12AW
1
D = 0.50
D = 0.20
D = 0.10
0.1
D = 0.05
D = 0.02
0.01 ^{D = 0.01}
SINGLE PULSE
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t, TIME (s)
10
100
Figure 7. Normalized Thermal Response
PACKAGE DIMENSIONS
A
SOT–363/SC–88
G
CASE 419B–02
ISSUE H
6
5
4
S
–B–
1
2
3
D 6 PL
C
0.2 (0.008) M B M
N
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
INCHES
DIM MIN MAX
A 0.071 0.087
B 0.045 0.053
C 0.031 0.043
D 0.004 0.012
G
0.026 BSC
H --- 0.004
J 0.004 0.010
K 0.004 0.012
N
0.008 REF
S 0.079 0.087
MILLIMETERS
MIN MAX
1.80 2.20
1.15 1.35
0.80 1.10
0.10 0.30
0.65 BSC
--- 0.10
0.10 0.25
0.10 0.30
0.20 REF
2.00 2.20
STYLE 20
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
H
K
1000
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NSL12AW/D