LC75879PT_13 Datasheet, PDF (4/35 Pages) ON Semiconductor – LCD Display Driver

1. When CL is stopped at the low level
CE
tφH
tφL
VIH1
CL ^50%
VIL1
tr
tf
VIH1
DI _VIL1
tds
tdh
LC75879PT
VIH1
tcp tcs
[Figure 2]
2. When CL is stopped at the high level
VIH1
CE
tφL
tφH
VIH1
CL
50%
VIL1
tf
tr
tcp tcs
DI
VIH1
VIL1
tds
tdh
[Figure 3]
3. OSCI pin clock timing in external clock operating mode
OSCI
VIH2
50%
VIL2
tCKH
tCKL
fCK =
1
tCKH+ tCKL
[kHz]
DCK=
tCKH
tCKH+ tCKL
×100[%]
[Figure 4]
VIL1
tch
VIL1
tch
No.A1687-4/35