LC75879PT_13 Datasheet, PDF (3/35 Pages) ON Semiconductor – LCD Display Driver

LC75879PT
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Symbol
Pin
Conditions
Ratings
Unit
min
typ
max
Hysteresis
Input high level current
VH
CE, CL, DI, INH
IIH1
CE, CL, DI, INH VI=6.3V
IIH2
OSCI
VI=VDD: External
clock operating mode
0.03VDD
V
5.0
μA
5.0
Input low level current
IIL1
CE, CL, DI, INH VI=0V
-5.0
IIL2
OSCI
VI=0V: External
-5.0
μA
clock operating mode
Output high level
VOH1 S1 to S69
IO=-20μA
VDD0-0.9
voltage *1
VOH2 COM1 to COM4 IO=-100μA
VDD0-0.9
V
VOH3 P1 to P8
IO=-1mA
VDD-0.9
Output low level
voltage
VOL1
VOL2
S1 to S69
COM1 to COM4
IO=20μA
IO=100μA
0.9
0.9
V
VOL3
P1 to P8
IO=1mA
0.9
Output middle level
voltage
VMID1 S1 to S69
1/3 bias IO=±20μA
2/3VDD0
-0.9
2/3VDD0
+0.9
*1
VMID2 S1 to S69
1/3 bias IO=±20μA
1/3VDD0
1/3VDD0
*2
-0.9
+0.9
V
VMID3 COM1 to COM4 1/3 bias IO=±100μA
2/3VDD0
2/3VDD0
-0.9
+0.9
VMID4 COM1 to COM4 1/3 bias IO=±100μA
1/3VDD0
-0.9
1/3VDD0
+0.9
Oscillator frequency
fosc
Internal
Internal oscillator
oscillator circuit operating mode
240
300
360 kHz
Current drain
IDD1
VDD
Power-saving mode
100
IDD2
VDD
VDD=6.3V
Output open
Internal oscillator
1000
2000
operating mode
IDD3
VDD
VDD=6.3V
μA
Output open
External clock
operating mode
1000
2000
fCK=300kHz
VIH2=0.5VDD VIL2=0.1VDD
Note: *1. VDD0=0.70VDD to VDD
Note: *2. Excluding the bias voltage generation divider resistors built in the VDD1 and VDD2. (See Figure 1.)
VDD
VDD1
VDD2
VSS
CONTRAST
ADJUSTER
VDD0
To the common and segment drivers
[Figure 1]
Except these resistors.
No.A1687-3/35