LC75879PT_13 Datasheet, PDF (21/35 Pages) ON Semiconductor – LCD Display Driver

LC75879PT
(10) FC0 to FC2 … Common/segment output waveform fram frequency control data
These control data bits set the frame frequency of the common and segment output waveforms.
Control data
Common/segment output waveform frame frequency fo[Hz]
FC0 FC1 FC2
Internal oscillator
operating mode
(The control data OC is 0,
fosc=300[kHz] typ)
External clock
operating mode
(The control data OC is 1
and EXF is 0,
fCK1=300[kHz] typ)
External clock
operating mode
(The control data OC is 1
and EXF is 1,
fCK2=38[kHz] typ)
1
1
0
fosc/6144
fCK1/6144
fCK2/768
1
1
1
fosc/4608
fCK1/4608
fCK2/576
0
0
0
fosc/3072
fCK1/3072
fCK2/384
0
0
1
fosc/2304
fCK1/2304
fCK2/288
0
1
0
fosc/1536
fCK1/1536
fCK2/192
0
1
1
fosc/1152
fCK1/1152
fCK2/144
1
0
0
fosc/768
fCK1/768
fCK2/96
Note: When is setting (FC0,FC1,FC2)=(1,0,1), the frame frequency is same as frame frequency at the time of the
(FC0,FC1,FC2)=(0,0,0) setting (fosc/3072, fCK1/3072, fCK2/384).
(11) CT0 to CT2 … Display contrast setting control data
These control data bits set display contrast.
CT0 to CT2: Sets the display contrast (7 steps)
CT0
CT1
CT2
LCD drive 3/3 bias voltage VDD0 level
0
0
0
1.00VDD=VDD-(0.05VDD×0)
1
0
0
0.95VDD=VDD-(0.05VDD×1)
0
1
0
0.90VDD=VDD-(0.05VDD×2)
1
1
0
0.85VDD=VDD-(0.05VDD×3)
0
0
1
0.80VDD=VDD-(0.05VDD×4)
1
0
1
0.75VDD=VDD-(0.05VDD×5)
0
1
1
0.70VDD=VDD-(0.05VDD×6)
Note: When is setting (CT0,CT1,CT2)=(1,1,1), the LCD drive 3/3 bias voltage VDD0 level is 1.00VDD.
Note that although the display contrast can be adjusted by operating the built-in display contrast
adjustment circuit, it can also be adjusted by modifying the supply pin VDD voltage level.
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