NOIL1SN3000A Datasheet, PDF (34/57 Pages) ON Semiconductor – MegaPixel High Speed CMOS Sensor

NOIL1SN3000A
IMAGE SENSOR TIMING AND READOUT
Pixel Timing
After every exposure cycle, the value on the pixel diode
is transferred to the pixel storage capacitor. This is
controlled by Vmem, precharge, and sample signals. The
duration of this operation is the FOT. At the beginning of the
FOT, Vmem is brought low, and precharge and sample are
brought high. The precharge pulse ensures that the old
information on the storage node is destroyed. This ensures
there is no image lag. After the falling edge of the precharge
pulse, the sampling operation on the storage node is
completed during the high level of sample.
After the falling edge of sample, Vmem is brought high.
The rise in Vmem compensates for the voltage loss in the last
source follower in the pixel. The readout begins after this.
The pulse length is controlled by the user. The registers that
control this are listed in the following section.
Considerations in Pixel Timing
The length of the FOT_TIMER, PRECHARGE_TIMER,
and SAMPLE_TIMER influences the final image quality.
• Precharge pulse: The pixel precharge prevents image
lag. A very short pulse results in image lag.
• Sample pulse: A shorter sample results in a reduced
dark level.
• FOT_TIMER register: The vmem signal must charge
all pixel storage capacitors simultaneously. This is a
large combined capacitance (96 nF) and Vmem takes
some time to stabilize. Readout must start only after
Vmem is stable.
The length of pixel_reset influences image lag. The pixel
must be reset for at least 3 ms.
Figure 22. Pixel Timing
Frame Rate and Windowing
Frame Rate
The frame rate depends on the input clock, FOT, and ROT.
The frame period is calculated as follows:
1 kernel = 32 pixels
1 granularity clock = 4 clock periods
Frame period = FOT + Nr. lines x (ROT + Nr. pixels/4 x
data period)
Or
Frame period = FOT + Nr. lines x (ROT + Nr. kernels *
granularity clock cycles)
Example
Readout time for full resolution at nominal speed of 206
MHz (4.854 ns) is given by
Frame period = 3.2 ms + (1710 x (176 ns + 1696/4 x 2.427
ns)) = 2.063 ms
Or
Frame period = 3.2 ms + (1710 x (176 ns + 53 x 19.4174
ns)) = 2.063 ms
Frame Rate = 485 fps
Alternatively, frame rate can also be expressed in terms of
reset length and integration time rather than readout time.
Table 46. CLARIFICATION OF FRAME RATE
PARAMETERS
Parameter
Comment
Clarification
FOT
Frame overhead
time
The FOT does a frame
transfer from pixel diode to
pixel storage node. During
this transfer, the sensor is
not read out. The FOT
length is programmable.
The default length is 3.2 ms.
ROT
Row overhead
time
The ROT transfers the pixel
output to the column amplifi-
ers. Default ROT is 176 ns.
Nr. lines
Number of lines
read out in each
frame
Default is 1710 lines.
Nr. pixels
Number of pixels
read out in each
line
Default is 1696 pixels.
Data period
0.5 x clock period
= 2.427 ns
Because the outputs oper-
ate at DDR, the data period
is half the clock period
(206 MHz clk).
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