NOIL1SN3000A Datasheet, PDF (27/57 Pages) ON Semiconductor – MegaPixel High Speed CMOS Sensor

NOIL1SN3000A
dly_sen, bits <3:0>
These bits allow adjusting the rising edge of the sensor
clock (CLK_SEN, clk/4) position, with respect to the high
speed input clock (clk) and the falling edge of the ADC
sample clock (ADC_CLK, clk/8).
Table 40. DLY_SEN BITS
Value
Effect
0000
Rising edge of CLK_SEN coincident with
falling edge of CLK_ADC
0001
CLK_SEN is +1 clk edge after falling edge of
CLK_ADC
0010
+2
0011
+3
0100
+4
0101
+5
0110
+6
0111
+7
1000
Same as code 0000
1001
CLK_SEN is –1 clk edge before falling edge of
CLK_ADC same as 0111
1010
–2 same as 0110
1011
–3 same as 1010
1100
–4 same as 0100
1101
–5 same as 0011
1110
–6 same as 0010
1111
–7 same as 0001
On startup
0000
dly_seq, bits <7:4>
These bits allow adjusting the falling edge of the sensor
odd/even select (CLK_SEQ, clk/8) position, with respect to
the high speed input clock (clk) and the falling edge of the
ADC sample clock (ADC_CLK, clk/8).
Table 41. DLY_SEQ BITS
Value
Effect
0000
Falling edge of CLK_SEQ coincident with
falling edge of CLK_ADC
0001
CLK_SEQ is +1 clk edge after falling edge of
CLK_ADC
0010
+2
0011
+3
0100
+4
0101
+5
0110
+6
0111
+7
1000
Same as code 0000
1001
CLK_SEQ is –1 clk edge before falling edge of
CLK_ADC
1010
–2
1011
–3
1100
–4
1101
–5
1110
–6
1111
–7
On startup
1100
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