NOIL1SN3000A Datasheet, PDF (11/57 Pages) ON Semiconductor – MegaPixel High Speed CMOS Sensor

NOIL1SN3000A
The ADCs are designed using fully differential circuits to
improve performance and noise immunity. In addition, a
redundant signed digit (RSD) 1.5 bit per stage architecture
with digital error correction is used to improve differential
nonlinearity (DNL) and ensure that no codes are missing.
Interstage ADC gain errors are addressed using
commutation techniques for capacitor matching.
Auto-zeroing and other calibration methods are
implemented to remove offsets.
References and Programmable Trimming
Bits 6:4 of SPI register 64 (decimal) allow adjustment of
the Vrefp-Vrefm differential ADC reference level. Eight
settings are provided to enable trimming of the dynamic
range. Reduced dynamic range is used to optimize signals in
low light intensity, where reduced pixel levels require
further gain. Table 10 provides the permitted trim settings.
Table 10. PROGRAMMABLE ADC REFERENCE
LEVEL
Register Address 64
(dec)
Bit 6 Bit 5 Bit 4
Vrefp-Vrefm
Gain Level
(typ)
Comments
000
0.5x
Maximum effective
gain +6.0 dB (2x)
001
0.67x
010
0.71x
011
0.77x
100
0.83x
101
0.91x
Available setting to
ensure 0 code
110
0.95x
Available setting to
ensure 0 code
111
1.0 x
POR (startup)
default level
The black voltage level from the pixel array is more
positive than the user set Vdark or “black” reference level.
This results in a nonzero differential voltage in the PGAs and
other AFE stages. This condition prevents obtaining a
desired 0 code out of the ADCs. The 0.95x and 0.91x trim
settings are specifically supplied to allow minor adjustment
to the ADC differential reference (Vrefp-Vrefm) to ensure a
zero level code in these conditions.
The additional trim settings are provided as dynamic
range adjustments in low light intensities to act as effective
global gain settings. The absolute level of gain (from the
typical values) is not guaranteed. However, the gain
increases are monotonic. Using this method, you can obtain
a maximum gain of approximately 2x (+6.0 dB). As a result,
the combined gain of both PGAs and the ADC reference
trimming available is 8x maximum.
Some reference voltages are overdriven after the on-chip
control logic is powered down (refer section On−Chip
BandGap Reference and Current Biasing on page 17).
Overdriving, a feature intended for testing and debugging,
is not recommended for normal operation. The reference
voltages that are overdriven are:
• Vrefp - Vrefm (can be overdriven as a pair)
• Vcm
• Vdark
• Internal bandgap voltage
Table 11 summarizes the ADC and AFE (signal
processing) parameters.
Each pair of odd and even kernel AFE + ADC channels are
individually powered down with its associated LVDS
serialization channel. This is controlled through bits in SPI
registers 66–70 (decimal). Logic 1 is the power down state.
The POR defaults are logic 0 for all channels powered on.
Table 11. AFE AND ADC PARAMETERS
Parameter
Parameter Value (typical)
Input range
1.5 V to 0.3 V
(single to differential converter; S2D) (SE to unipolar differential)
Vblack
1.2 V to 1.5 V (typical)
Analog PGA gain and settings
Input range (ADC)
ADC type
ADC resolution
Sampling rate per ADC
ENOB
Differential nonlinearity (DNL)
Integral nonlinearity (INL)
Power supply
1x to 4x (6 gain settings)
0.75 V to 1.75 V
Pipelined (four ADC clock latency)
8 bits
26.5 MSPS
7.5 bits
±0.5 LSB
±1.0 LSB
2.5 V ±0.25 V
Comment
S2D performs inversion. Referenced from Vblack
Dark or black level reference from SPI programmable
DAC. 0.01 mF to gnd
3-bit SPI programmable. 1x, 1.5x, 2x, 2.25x, 3x, 4x
1 V maximum Vrefp-Vrefm (2 Vp-p maximum)
With digital error correction (no missing codes)
Maximum 30 MSPS
Effective number of bits
No missing codes
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