LC88F5LA4ACS Datasheet, PDF (30/33 Pages) Sanyo Semicon Device – FROM 96K byte, RAM 6K byte on-chip 16-bit 1-chip Microcontroller

LC88F5LA4ACS
Characteristics of a Sample OSC1 System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator
Nominal
Frequency
Vendor
Name
Resonator
Circuit Constant
Operating
Voltage
Oscillation
Stabilization Time
C3
C4
Rf
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[ms]
[ms]
Remarks
10MHz
CSTCE10M0G52-R0 (10)
(10) OPEN
0
2.2 to 3.6
0.02
C1, C2
0.2
integrated type
8MHz
MURATA CSTCE8M00G52-R0 (10)
(10) OPEN
0
2.2 to 3.6
0.02
C1, C2
0.2
integrated type
4MHz
CSTCR4M00G53-R0 (15)
(15) OPEN 680
2.2 to 3.6
0.02
C1, C2
0.2
integrated type
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the lower limit level of the operating voltage range (see Figure 4)
Characteristics of a Sample System Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Resonator
Nominal
Frequency
Vendor
Name
Oscillator Name
Circuit Constant
Operating
Voltage
Oscillation
Stabilization Time
C3
C4
Rf2
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
Remarks
32.768kHz
EPSON
TOYOCOM
MC-306
18
18 OPEN
0
2.2 to 3.6
0.9
Applicable
2
CL value=12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillator circuit is executed plus the time interval that is required for the oscillation
to get stabilized after the HOLD mode is released (see Figure 4).
Note: The traces to and from the components that are involved in oscillation should be kept as short as possible as the
oscillation characteristics are affected by their trace pattern.
CF1
Rf1
C1
CF
CF2
Rd1
C2
Figure 1 CF Oscillator Circuit
XT1
XT2
Rf2
Rd2
C3
C4
X’tal
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A1860-30/33