CAT34TS02 Datasheet, PDF (3/22 Pages) ON Semiconductor – Digital Output Temperature Sensor with On-board SPD EEPROM

A.C. CHARACTERISTICS⁽¹⁾
V_CC = 3.3 V ± 10%, T_A = −40°C to +125°C
Symbol
F_SCL(2)
t_HIGH
t_LOW
t_TIMEOUT(2)
t_R(3)
t_F(3)
t_SU:DAT(4)
t_HD:DAT(3)
t_SU:STA
t_HD:STA
t_SU:STO
t_BUF
T_i
t_WR
t_PU(5)
Parameter
Clock Frequency
High Period of SCL Clock
Low Period of SCL Clock
SMBus SCL Clock Low Timeout
SDA and SCL Rise Time
SDA and SCL Fall Time
Data Setup Time
Data Hold Time (for Input Data)
Data Hold Time (for Output Data)
START Condition Setup Time
START Condition Hold Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
Noise Pulse Filtered at SCL and SDA Inputs
Write Cycle Time
Power-up Delay to Valid Temperature Recording
CAT34TS02
Min
10
600
1300
25
100
0
300
600
600
600
1300
Max
400
35
300
300
900
100
5
100
Units
kHz
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
PIN CAPACITANCE
T_A = 25°C, V_CC = 3.3 V, f = 1 MHz
Symbol Parameter
SDA, E¯¯V¯E¯N¯T¯ Pin Capacitance
C_IN
Input Capacitance (other pins)
Test Conditions/Comments
V_IN = 0
V_IN = 0
Min
Max
Unit
8
pF
6
pF
Notes:
(1) Timing reference points are set at 30%, respectively 70% of VCC, as illustrated in Figure 4. Bus loading must be such as to allow meeting
the VIL, VOL as well as the various timing limits.
(2) The TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the tTIMEOUT limit. The time-out count is
started (and then re-started) on every negative transition of SCL in the time interval between START and STOP. The minimum clock
frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency for the CAT34TS02’s SPD component is DC,
while the minimum operating frequency for the TS component is limited only by the SMBus time-out.
(3) In a “Wired-OR” system (such as I²C or SMBus), SDA rise time is determined by bus loading. Since each bus pull-down device must be
able to sink the (external) bus pull-up current (in order to meet the VIL and/or VOL limits), it follows that SDA fall time is inherently faster
than SDA rise time. SDA rise time can exceed the standard recommended tR limit, as long as it does not exceed tLOW - tHD:DAT - tSU:DAT,
where tLOW and tHD:DAT are actual values (rather than spec limits). A shorter tHD:DAT leaves more room for a longer SDA tR, allowing for a
more capacitive bus or a larger bus pull-up resistor. At the minimum tLOW spec limit of 1300 ns, the maximum tHD:DAT of 900 ns demands a
maximum SDA tR of 300 ns. The CAT34TS02’s maximum tHD:DAT is <700 ns, thus allowing for an SDA tR of up to 500 ns at minimum tLOW.
(4) The minimum tSU:DAT of 100 ns is a limit recommended by standards. The CAT34TS02 will accept a tSU:DAT of 0 ns.
(5) The first valid temperature recording can be expected after tPU at nominal supply voltage.
© 2010 SCILLC. All rights reserved.
3
Characteristics subject to change without notice
Doc. No. MD-1129 Rev. G