CAT34TS02 Datasheet, PDF (14/22 Pages) ON Semiconductor – Digital Output Temperature Sensor with On-board SPD EEPROM

CAT34TS02
TEMPERATURE SENSOR OPERATION
The TS component in the CAT34TS02 combines a
Proportional to Absolute Temperature (PTAT)
sensor with a ∑ -Δ modulator, yielding a 12 bit plus
sign digital temperature representation.
The TS runs on an internal clock, and starts a new
conversion cycle at least every 100 ms. The result of
the most recent conversion is stored in the
Temperature Data Register (TDR), and remains
there following a TS Shut-Down. Reading from the
TDR does not interfere with the conversion cycle.
The value stored in the TDR is compared against
limits stored in the High Limit Register (HLR), the
Low Limit Register (LLR) and/or Critical
Temperature Register (CTR). If the measured
value is outside the alarm limits or above the critical
limit, then the E¯¯V¯E¯N¯T¯ pin may be asserted. The
E¯¯V¯E¯N¯T¯ output function is programmable, via the
Configuration Register for interrupt mode,
comparator mode and polarity.
The temperature limit registers can be Read or
Written by the host, via the serial interface. At
power-on, all the (writable) internal registers default
to 0x0000, and should therefore be initialized by the
host to the desired values.The E¯¯V¯E¯N¯T¯ output starts
out disabled (corresponding to polarity active low);
thus preventing irrelevant event bus activity before
the limit registers are initialized. While the TS is
enabled (not shut-down), event conditions are
normally generated by a change in measured
temperature as recorded in the TDR, but limit
changes can also trigger events as soon as the new
limit creates an event condition, i.e. asynchronously
with the temperature sampling activity.
In order to minimize the thermal resistance between
sensor and PCB, it is recommended that the
exposed backside die attach pad (DAP) be soldered
to the PCB ground plane.
REGISTERS
The CAT34TS02 contains eight 16-bit wide registers
allocated to TS functions, as shown in Table 3. Upon
power-up, the internal address counter points to the
capability register.
Capability Register (User Read Only)
This register lists the capabilities of the TS, as
detailed in the corresponding bit map.
Configuration Register (Read/Write)
This register controls the various operating modes of
the TS, as detailed in the corresponding bit map.
Temperature Trip Point Registers (Read/Write)
The CAT34TS02 features 3 temperature limit
registers, the HLR, LLR and CLR mentioned earlier.
The temperature value recorded in the TDR is
compared to the various limit values, and the result
is used to activate the E¯¯V¯E¯N¯T¯ pin. To avoid
undesirable E¯¯V¯E¯N¯T¯ pin activity, this pin is
automatically disabled at power-up to allow the host
to initialize the limit registers and the converter to
complete the first conversion cycle under nominal
supply conditions. Data format is two’s complement
with the LSB representing 0.25°C, as detailed in the
corresponding bit maps.
Temperature Data Register (User Read Only)
This register stores the measured temperature, as
well as trip status information. B15, B14, and B13
are the trip status bits, representing the relationship
between measured temperature and the 3 limit
values; these bits are not affected by EVENT status
or by Configuration register settings. Measured
temperature is represented by bits B12 to B0. Data
format is two’s complement, where B12 represents
the sign, B11 represents 128°C, etc. and B0
represents 0.0625°C.
Manufacturer ID Register (Read Only)
The manufacturer ID assigned by the PCI-SIG trade
organization to the CAT34TS02 device is fixed at
0x1B09.
Device ID and Revision Register (Read Only)
This register contains manufacturer specific device
ID and device revision information.
Doc. No. MD-1129 Rev. G
14
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Characteristics subject to change without notice