CAT34TS02 Datasheet, PDF (1/22 Pages) ON Semiconductor – Digital Output Temperature Sensor with On-board SPD EEPROM

Digital Output Temperature Sensor with
On-board SPD EEPROM
CAT34TS02
FEATURES
 JEDEC JC42.4 Compliant Temperature Sensor
 Temperature Range: - 40°C to +125°C
 DDR3 DIMM compliant SPD EEPROM
 Supply Range: 3.3 V ± 10%
 I²C / SMBus Interface
 Schmitt Triggers and Noise Suppression Filters
on SCL and SDA Inputs
 Low Power CMOS Technology
 RoHS-compliant 2 x 3 x 0.75 mm TDFN package
For Ordering Information details, see page 21.
PIN CONFIGURATION
TDFN (VP2)
(2 x 3 x 0.75 mm)
A₀ 1
A₁ 2
A₂ 3
V_SS 4
8 V_CC
7 EVENT
6 SCL
5 SDA
Note: For the location of Pin 1, please consult the corresponding
package drawing.
PIN FUNCTIONS
Name
A₀, A₁, A₂
SDA
SCL
E¯¯V¯E¯N¯T¯
V_CC
V_SS
DAP
Description
Device Address Input
Serial Data Input/Output
Serial Clock Input
Open-drain Event Output
Power Supply
Ground
Backside exposed DAP at V_SS
DESCRIPTION
The CAT34TS02 combines a JC42.4 compliant
Temperature Sensor (TS) with 2-Kb of Serial
Presence Detect (SPD) EEPROM.
The TS measures temperature at least 10 times every
second. Temperature readings can be retrieved by the
host via the serial interface, and are compared to
high, low and critical trigger limits stored into internal
registers. Over or under limit conditions can be
signaled on the open-drain E¯¯V¯E¯N¯T¯ pin.
The integrated 2-Kb SPD EEPROM is internally
organized as 16 pages of 16 bytes each, for a total of
256 bytes. It features a 16-byte page write buffer and
supports both the Standard (100 kHz) as well as Fast
(400 kHz) I²C protocol.
Write operations to the lower half memory can be
inhibited via software commands. The CAT34TS02
features Permanent, as well as Reversible Software
Write Protection, as defined for DDR3 DIMMs.
FUNCTIONAL SYMBOL
V_CC
SCL
A₂, A₁, A₀
SDA
CAT34TS02
V_SS
EVENT
© 2010 SCILLC. All rights reserved.
1
Characteristics subject to change without notice
Doc. No. MD-1129 Rev. G