CAT34TS02 Datasheet, PDF (16/22 Pages) ON Semiconductor – Digital Output Temperature Sensor with On-board SPD EEPROM

CAT34TS02
CONFIGURATION REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
RFU
RFU
RFU
RFU
RFU
HYST [1:0]
SHDN
B7
B6
B5
B4
B3
B2
B1
B0
TCRIT_LOCK EVENT_LOCK CLEAR EVENT_STS EVENT_CTRL TCRIT_ONLY EVENT_POL EVENT_MODE
Bit
B15:B11
B10:B9⁽¹⁾
B8 ⁽⁵⁾
B7 ⁽⁴⁾
B6 ⁽⁴⁾
B5 ⁽³⁾
B4 ⁽²⁾
B3 ⁽¹⁾
B2 ⁽⁷⁾
B1 ^{(1), (6)}
B0 ⁽¹⁾
Description
Reserved for future use ; can not be written ; should be ignored; will read as 0
00: Disable hysteresis
01: Set hysteresis at 1.5°C
10: Set hysteresis at 3°C
11: Set hysteresis at 6°C
0: Thermal Sensor is enabled; temperature readings are updated at sampling rate
1: Thermal Sensor is shut down; temperature reading is frozen to value recorded before SHDN
0: Critical trip register can be updated
1: Critical trip register cannot be modified; this bit can be cleared only at POR
0: Alarm trip registers can be updated
1: Alarm trip registers cannot be modified; this bit can be cleared only at POR
0: Always reads as 0 (self-clearing)
1: Writing a 1 to this position clears an event recording in interrupt mode only
0: EVENT output pin is not being asserted
1: EVENT output pin is being asserted
0: EVENT output disabled; polarity dependent: open-drain for B1 = 0; grounded for B1 = 1
1: EVENT output enabled
0: event condition triggered by alarm or critical temperature limit crossing
1: event condition triggered by critical temperature limit crossing only
0: EVENT output active low
1: EVENT output active high
0: Comparator mode
1: Interrupt mode
Notes:
(1) Can not be altered (set or cleared) as long as either one of the two lock bits, B6 or B7 is set.
(2) This bit is a polarity independent ‘software’ copy of the E¯¯V¯E¯N¯T¯ pin, i.e. it is under the control of B3.
(3) Writing a ‘1’ to this bit clears an event condition in Interrupt mode, but has no effect in comparator mode. When read, this bit always
returns 0. Once the measured temperature exceeds the critical limit, setting this bit has no effect (see Figure 5).
(4) Cleared at power-on reset (POR). Once set, this bit can only be cleared by a POR condition.
(5) The TS powers up into active mode, i.e. this bit is cleared at power-on reset (POR). When the TS is shut down the ADC is disabled and
the temperature reading is frozen to the most recently recorded value. The TS can not be shut down (B8 can not be set) as long as either
one of the two lock bits, B6 or B7 is set. However, the bit can be cleared at any time.
(6) The E¯¯V¯E¯N¯T¯ output is “open-drain” and requires an external pull-up resistor for either polarity. The “natural” polarity is “active low”, as it
allows “wired-or” operation on the EVENT bus.
(7) Can not be set as long as lock bit B6 is set.
Doc. No. MD-1129 Rev. G
16
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Characteristics subject to change without notice