LC88F85D0A Datasheet, PDF (24/31 Pages) Sanyo Semicon Device – FROM 256K byte, RAM 8K byte on-chip 16-bit 1-chip Microcontroller

LC88F85D0A
Continued from preceding page.
Parameter
HALT mode
consumption
current
(Note 7-2)
Symbol
Pin/
Remarks
Conditions
VDD[V]
min
IDDHALT(1)
VDD
HALT mode
• FOSC0=32.768kHz
LCD
display
2.0 to 5.5
IDDHALT(2)
• System clock set to FOSC0 side
ON
• Internal RC oscillation stopped
2.0 to 3.6
IDDHALT(3)
• FOSC1=0Hz (oscillation stopped)
• Frequency division ratio set to 1/1
LCD
display
2.0 to 5.5
IDDHALT(4)
• Normal XT mode
[No panel load]
OFF
2.0 to 3.6
IDDHALT(5)
IDDHALT(6)
IDDHALT(7)
IDDHALT(8)
HALT mode
• FOSC0=32.768kHz
• System clock set to FOSC0 side
• Internal RC oscillation stopped
• FOSC1=0Hz (oscillation stopped)
• Frequency division ratio set to 1/1
• Low power XT mode
[No panel load]
LCD
display
ON
LCD
display
OFF
2.0 to 5.5
2.0 to 3.6
2.0 to 5.5
2.0 to 3.6
Specification
typ
max
unit
45
110
16
50
36
90
7.8
51
μA
15.5
53
12
30
6.5
40
4
30
IDDHALT(9)
HALT mode
• FmCF=10MHz ceramic oscillator
• FOSC0=0Hz (oscillation stopped)
• System clock set to 10MHz side
4.5 to 5.5
2.0
3.4
• Internal RC oscillation stopped
• Frequency division ratio set to 1/1
IDDHALT(10)
HALT mode
• FmCF=8MHz ceramic oscillator
• Internal RC oscillation stopped
4.5 to 5.5
1.7
2.9
IDDHALT(11)
• FOSC0=0Hz (oscillation stopped)
• System clock set to 8MHz side
• Internal RC oscillation stopped
3.0 to 4.5
1.2
2.1
• Frequency division ratio set to 1/1
IDDHALT(12)
HALT mode
• FmCF=4MHz ceramic oscillator
4.5 to 5.5
0.7
1.2
IDDHALT(13)
• FOSC0=0Hz (oscillation stopped)
• System clock set to 4MHz side
• Internal RC oscillation stopped
2.2 to 4.5
mA
0.3
0.85
• Frequency division ratio set to 1/2
IDDHALT(14)
HALT mode
• System clock set to internal RC side
2.0 to 5.5
0.7
1.3
• Internal RC oscillation oscillated
IDDHALT(15)
• FOSC0=0Hz (oscillation stopped)
• FOSC1=0Hz (oscillation stopped)
2.0 to 3.6
0.3
0.6
• Frequency division ratio set to 1/1
IDDHALT(16)
HALT mode
• FOSC1=1MHz RCR1=470kΩ
• System clock set to FOSC1 side
2.0 to 5.5
0.2
0.5
IDDHALT(17)
• Internal RC oscillation stopped
• FOSC0=0Hz (oscillation stopped)
• Frequency division ratio set to 1/1
2.0 to 3.6
0.1
0.3
*Ta=0 to 60°C
IDDHALT(18)
HALT mode
• FOSC0=64kHz RCR0=910kΩ
• System clock set to FOSC0 side
2.0 to 5.5
20
60
IDDHALT(19)
• Internal RC oscillation stopped
• FOSC1=0Hz (oscillation stopped)
• Frequency division ratio set to 1/1
2.0 to 3.6
μA
10
40
*Ta=0 to 60°C
Note 7-2: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A1954-24/31