LC88F85D0A Datasheet, PDF (21/31 Pages) Sanyo Semicon Device – FROM 256K byte, RAM 8K byte on-chip 16-bit 1-chip Microcontroller

Continued from preceding page.
Parameter
Symbol
Stop condition
setup time
tSU;STO
LC88F85D0A
Pin/Remarks
Conditions
SM0CK(P22)
SM0DA(P23)
• See Fig. 8.
VDD[V]
Specification
min
typ
max
Unit
1.0
Tfilt
tSU;STOx SM0CK(P22) • Standard clock mode
SM0DA(P23)
• Specified as the time up to
the beginning of output
2.0 to 5.5
4.9
change.
• High-speed clock mode
μs
• Specified as the time up to
the beginning of output
1.1
change.
Data hold time
tHD;DAT
SM0CK(P22) • See Fig. 8.
SM0DA(P23)
0
tHD;DATx SM0CK(P22) • Specified as the time up to
2.0 to 5.5
SM0DA(P23)
the beginning of output
1
change.
Data setup time
tSU;DAT
SM0CK(P22) • See Fig. 8.
SM0DA(P23)
1
Tfilt
1.5
SM0CK, SM0DA
pin fall time
tSU;DATx
tF
SM0CK(P22)
SM0DA(P23)
SM0CK(P22)
SM0DA(P23)
• Specified as the time up to
the beginning of output
change.
• See Fig. 8.
2.0 to 5.5
2.0 to 5.5
1tSCL-
1.5Tfilt
Tfilt
300
tF
SM0CK(P22) • When SMIIC register control
SM0DA(P23)
bits PSLW=1, P5V=1
5
20+0.1Cb
250
• When SMIIC register control
bits PSLW=1, P5V=0
3
20+0.1Cb
250
ns
• When SM0CK and SM0DA
port outputs are placed in
fast mode
3.0 to 5.5
100
• Cb≤400pF
Note 4-4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Note 4-4-2: Tfilt denotes the value that is determined by the values of register SMIC0BRG, bits 7 and 6 (BRP1, BRP0)
and the system clock frequency.
BRP1
BRP0
Tfilt
0
0
tCYC×1
0
1
tCYC×2
1
0
tCYC×3
1
1
tCYC×4
Set up (BPR1, BPR0) so that Tfilt falls within the following range:
250ns ≥ Tfilt > 140ns
Note 4-4-3: Cb denotes the total capacitance (in pF) of the loads connected to each bus. Cb ≤ 400pF
Note 4-4-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG within the following
ranges:
250ns ≥ Tfilt > 140ns
BRDQ (bit 5) = 1
SCL frequency setting ≤ 100kHz
The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250ns ≥ Tfilt > 140ns
BRDQ (bit 5) = 0
SCL frequency setting ≤ 400kHz
No.A1954-21/31