SCYW99143 Datasheet, PDF (22/35 Pages) ON Semiconductor – Universal High Voltage Control Block

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NOT FOR PUBLIC RELEASE
SCYW99143
point I and startup current source is enabled again to charge
Vcc capacitor up − to Vcc_on level. The PWM block is
enabled at point J together with remote pull down switch and
timer (point K). Application then operates regularly in
PWM mode.
An overload condition occurs on the output in point L.
The slave controller fault timer counts down the 100 ms
period (fault timer duration is parameter of slave controller)
before it disables PWM block internally (point M). The Vcc
collapses due to controller consumption and passes Vcc_off
threshold where 1 s auto−recovery timer is activated and
PWM_ON signal is deactivated (point N). The Vcc is again
maintained at Vcc_bias level when auto−recovery timer
counts down the off− time. Application is suddenly
unplugged from the mains (point O) before the
auto−recovery timer elapses. The X2 timer is activated after
X2 pin voltage drops (point P). The controller does not allow
new attempt for restart when X2 timer is counting even the
auto−recovery timer elapses. The X2 capacitor is then
discharged after X2 timer elapses (point Q).
Note that auto−recovery timer is starter after Vcc_off
threshold is reached AND remote pin is at low level – i.e.
application felt into fault during PWM block operation. The
remote input is ignored and new restart is placed after
auto−recovery timer elapses.
5. Application start, latch−off after 120 ms, AC line
restart – Figure 50:
Application operation from point A to point E is the same
like in 1^st case described in paragraph 1. The controller
however latches−off approximately 120 ms after startup in
this case – point F. Controller can be latched by various
mechanisms – refer below to descriptions. The PWM block
is disabled internally after latch has been asserted. The Vcc
capacitor is discharged by Vcc discharge switch to Vcc_bias
level. The Vcc_bias (5 V) is then maintained by HV startup
current source to keep controller in latched state.
The user recognized that SMPS is not working and tries
to restart it by re−plugging into the mains. Thus the
application is unplugged at point G. The X2 discharge timer
is activated via X2 pin (point H). The X2 capacitor is
discharged and all Vcc is lost after X2 timer elapses (point
I). The internal logic is thus reset and prepared for next start
attempt.
User plugs application into the mains again at point J.
Standard startup sequence occurs (including remote pull
down switch and timer activation). Application then
operates in normal operating modes (e.g. standard PWM
operation, frequency foldback or skip mode).
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